Search the Community

Showing results for tags 'constraint'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 4 results

  1. Djsnzheusj

    ARTY A7-35 REV E.

    Hello guys, Im still starting off with FPGA's and i wonder if any one can point me to where the XDC file can be obtained for my board ARTY A7-35 REV E. the only master file i find is for the REV.D will it make a difference ? Thank you so much in advance.
  2. I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset. I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots). I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files. Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions. mig.prj board.xml part0_pins.xml preset.xml
  3. aladinsane

    Basys3 lighting leds

    I'm a beginner to fpga programming and working on BASYS3. In my System Verilog code I have 2 2 bit outputs: la and lb. Assuming these are two traffic lights and 00 means red, 10 means yellow, 11 means green. If output is red, 3 leds will light. But I don't know how to implement it in constraint file. Normally, when an output is 1, I want to led to light and I write this kind of code: set_property PACKAGE_PIN U14 [get_ports {la[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {la[0]}] But this time I want the led to light when output 0. Maybe I can write 2 more outputs that will become the opposite of my real outputs and I can use them in constraint but I wonder can I directly implement what I want in constraint file.
  4. Mehdim

    how to define constraint

    Hello guys; Can anyone help me how to assign a port to specific pin in Vivado? I am using custom port on AX_GPIO module and I want to add it to one of PMOD connectors; I am using this command to connect it to V12 set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { gpio2_io_o }]; it works fine, but if I want to assign a vector port to some pins(for example gpio2_io_o[7:0] ) what should I do to define constraint?