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Found 13 results

  1. Can you please create statement of volatility docs for Cmod A7-15T and Cmod A7-35T, similar to the thread below.
  2. Hello Digilent Forum! I have been able to run the Cmod A7 Out of Box Demo and export it to an SDK/Vitis project, then modify memorytest.c to write and read new data to and from the SRAM. What a great demo for getting started with the Cmod A7! However, I would like to configure the external memory controller (AXI EMC) block to use its individual ports -- without using the Cmod A7 board file and the "cellular_ram" port from the EMC_INTF pin of the EMC block. I created a new project that uses the xc7a35tcpg236-1 FPGA (not the board file), edited the constraints XDC file, and pinned out the EMC block to match the specs of the onboard ISSI IS61WV5128 SRAM; but it fails to generate a bitstream file successfully. I have also tried to setup tristate buffers (IOBUF) at the top level similar to the demo project's user_35t_wrapper.v file does, but no luck. Configuring the EMC signals (mem_dq_i, mem_dq_o, mem_dq_t, mem_dq_io) for a tristate buffer to interface with the SRAM's data lines seems to be the most confusing part. An image of what I "think" the EMC block should look like is attached. Any help interfacing the EMC block and SRAM correctly (without the board file) would be greatly appreciated. Thanks! Ian
  3. PTSmith

    CMOD A7 100 MHz clock in

    So, I want to bring in a 100 MHz clock and route it to a CMT to generate a bunch of lower frequency clocks all phase-locked to the 100 MHz. I appreciate I can't output an LVDS signal, but it looks like I should be able to bring in an LVDS signal as long as I supply my own 100 ohm termination to pins 18 and 19 for example. Am I missing anything? Paul Smith Indiana University Physics
  4. Hi all, i tryed to do the "How To Store Your SDK Project in SPI Flash" tutorial but i do not get it to work. Everything seems to be successful, but after rebooting the CmodA7 the .elf program i created does not start. During creating the project i followed the instruction from the attached post. ( Additional i tryed to merge the .bit and .elf file with Vivado like the tutorial ( Programming the fpga manual works, but if i try to write it in the flash the .elf program does not start. After programing the flash the bitstream is out of date (i don't know why). Maybe someone have an idea what i can do to get the merged bit file or mcs file on the spi-flash? Attached is my vivado project folder (
  5. Regarding the the board Artix-7 (CMOD-A7) - The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.
  6. Hi All, I'm start working with the AXI UART Lite in my Block Design with a Microblaze soft core. Actually I've the whole design working, using the xil_printf I'm able to send data out the board to the PC through the Virtual COM Port exposed by the board itself. The better approach involve the use of interrupts in order to manage the RX and TX operations. My first try was to found some documents about this point, found it into the yourdesign_bsp > BSP Documentation > uartlite_v3_2 folder: right click and select Open Documentation give the API list on the browser, the documentation reside locally on the following path (I'm using VIVADO 2016.1): C:/Xilinx/SDK/2016.1/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_2/doc/html/api/index.html Opening the: C:/Xilinx/SDK/2016.1/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_2 inside the examples there are several examples how to use interrupt with this peripheral, I took the xuartlite_intr_tapp_example.c file. Concerning this example I've some question to asking. Looking through the source code I see: #ifdef XPAR_INTC_0_DEVICE_ID #include "xintc.h" #include <stdio.h> #else #include "xscugic.h" #include "xil_printf.h" #endif First question is about this conditional statement. Starting from the SDK I've opened the xparameters.h file: scroll down until you reach the xparameters.h file. Double click on to open the file and make a search for the XPAR_INTC_0_DEVICE_ID label: This label should be the reference to the AXI Interrupt Controller present into the Block Design (system.pdf).with name microblaze_0_axi_intc. Now I need to know the exact difference between this two type of controller, the AXI is into the Fabric and I think is automatically managed from the Microblaze side by means of a dedicated software layer also the Generic Interrupt Controller I think is also managed by Microblaze but may be I've to configure it in order to instruct what peripheral have to use I'm correct? In this example I'm using the AXI Interrupt Controller so I can avoid to insert the whole code related the Generic Interrupt Controller, correct? Another question is if I'm using the AXI Interrupt Controller there are some reason to use also the Generic Interrupt Controller or I can't use it due to some constraints or other reasons? Someone can give me some explanation about this point? Thank!
  7. I am using Vivado 2017.4 and using the download.bit image (and .elf file with offset) with the "Program Flash Memory" function in SDK. This follows your MicroBlaze tutorial and has been working well using the same CmodA7 module. I've bought several of these and when I connected a different one there have been a few issues. Using Windows 7 64 bit, the first time a new module is plugged in, it has to install it as a new device. This makes Device Mangler assign a new Com port number to it. Sometimes Windows thinks it's some kind of electronic pen and I've had to delete the driver and let it install again. This is being done automatically by Windows. So, the first question is whether there is a better way to install these? I guess there's no way around having Windows recognize each one of these as different devices? Next, if I have Vivado and SDK up and running and try to program the flash it fails and errors because it can't find the device to program. I went into Vivado and used the Hardware Manager to find new hardware. It did this okay but then going back to SDK and trying to program the flash it fails to find the device. So I closed SDK and reopened it and tried this again but this doesn't work either. Closing SDK and Vivado and then reopening then both, SDK now recognizes and programs the new device successfully. I've had to close both and then reopen them for each device. The above was done with devices that I had already managed to install once before. A completely new device seems to require setting the flash device type again in the programming utility but SDK seems to remembers that the next time that device is plugged in. I have a few more CmodA7 modules on order for some further prototyping and am wondering if there is a more streamlined way to work with these?
  8. First of all I want to apolagize if my questions sound a little bit dumb, I'm not familiar with FPGA's. To give a little bit of context, my project consists in generate a digital signal (a triangular signal, close to a sawtooth) through an FPGA (Cmod A7) and then convert it with a DAC. The signal won't be static, i.e. the user should be able to change its slope. So for the user to change the slope, I need an interface to control some register. My question is exactly this, is there any interfaces available to write on registers in real time? I intended to use LabView with this interface but unfortunately I'm not being able to connect the FPGA with this, so I'm looking for alternatives.
  9. The CmodA7-35T uses a N25Q032 flash. This provides sufficient room for the bit file and a little less than half of it for something else like an elf load. If two bit loads were desired such as for a multi boot reconfiguration with a golden load and a field installed load there would not be sufficient room to do this. Perhaps compressing the bit files might be a way to still make that work. I was looking at this line of flash devices and noticed that there is a general trend toward the lower sizes becoming less available or obsolete and the cost for larger sizes aren't much more than the smaller ones now. In particular the 032 and 064 seem to be going away. With that, is there any plan to use larger size flash devices for this product in the future?
  10. Hello. I was able to follow the example "How To Store Your SDK Project in SPI Flash". My new problem is that I want to drive a second SPI device using that QSPI port. Should I share that existing QSPI port with my new external slave device, or implement another AXI_Quad_SPI block? Now I'm forced to ask, how does Vivado (or SDK) know where the MISO, MOSI, SCLK and Slave Select lines are for the memory device? Vivado generated an XDC file with only one line ("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"), yet it works just fine to download from the external flash memory (CMod-A7 board). There must be another file that has this board information. I'm calling this an "invisible constraint file". Do I use the actual constraint file to set my SPI port pin assignments for my second port? If so, wouldn't that "invisible constraint file" interfere? If recommended to use 1 SPI port to drive the 2 slaves, then how do I implement the Slave Select signals? Are there any SPI examples with multiple slaves to demonstrate this? Thank you, Richard V
  11. I spotted a question on Stack Exchange's electronics forum regarding symbols in the A7's schematic … I'm not the original poster, but I'm now very curious too – what do those coloured blocks on certain groups of pins mean?
  12. Hi,Even though I think this board should be towards questions about Digilent boards specifically, see if you can help me (I tried Xilinx forums without success). I am using the XADC's Vaux4 and Vaux12 on my Cmod A7. However, I'm having difficulties implementing the simultaneous sampling function using the XADC Wizard (Vivado 2016.2). From the wizard I get the ADC module with one address_in "pin" and one data_out "pin". My question is, if it is sampling both pairs simultaneously, how do I access the data? Wouldn't it be necessary to have two data outputs, one for each pair? How does it work? Thank you guys for your time and patience,Leo
  13. Hi, I'm having a problem programming di EEPROM of the FT2232HQ on my Digilent CMOD A7 35T board with FT_PROG, I hope someone can help. I wanted to change the hardware and the drivers of the A port to UART and VCP respectivly. After that, noticing that I couldn't program the FPGA with Vivado anymore, I re-programmed the FTDI with FT_PROG to its initial state (port A with 245FIFO hardware and D2XX Direct drivers), but I'm still not able to program the FPGA with Vivado because it seems to not recognize any hardware target. It seems that the FTDI is not able to connect to and to control the JTAG circuitry anymore. I must say that first of all I also created a template of the EEPROM in order to have a stable state to which return in any case.Isn't there a way to program the FTDI to its inital (factory) state?