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Found 23 results

  1. create delay in verilog in cmod a7

    hello, i am using cmod a7. i am trying to blink the led at 1 sec delay(using verilog language). please help me with the code and also let me know the frequency we will be using to create delay and at which pin will it be available.
  2. I have an Arty-35 evaluation board that came with a device-locked, node-locked Vivado license. (BTW, the board and tools are very nice). Does my limited Vivado license also cover programming the Cmod A7: Breadboardable Artix-7 FPGA Module which also uses an Artix-7 A7-35T FPGA component? I think they're the same Artix-7 device, so it seems like it should work. I'd like to purchase one of these Cmod A7 FPGA DIP devices, but I want to be sure my Vivado license will cover it.
  3. ethernet with cmod A7

    hello, i want to know whether or not it is possible to connect ethernet port to CMOD A7. as number of input output lines are restricted .if yes then how?
  4. Hi folks, I'm using some very basic examples with Cmod A7, which work in the sense that they result in a behaving FPGA. However, I'm trying to get rid of, or at, least understand the various warnings. One warning that occurs for all examples I tried is: CFGBVS-1#1 Warning Missing CFGBVS and CONFIG_VOLTAGE Design Properties Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: ... OK, I see where to set them in the Tools > Edit Device Properties window, but I'm not sure what to set them to for the Cmod A7. Available values are: CONFIG_VOLTAGE: 1.5, 1.8, 2.5, 3.3 CFGBVS (Configuration Bank Voltage Selection): GND, VCC0 ... but I'm not too inclined to just experiment with different values, for fear of doing some damage. (Though somehow, the default blank settings appear to work, other than the warning message.) Questions: Do these settings set something in the FPGA configuration, or do they merely inform Vivado of the hardware's design? Does the specific wiring of this board impose/require only certain values for these items, or can alternatives be chosen? What is/are those settings, and under what circumstances do you use them? This appears to relate: https://www.xilinx.com/support/answers/57045.html. Also ug470_7series_Config.pdf, "Configuration Banks Voltage Select" section. I note on the Cmod A7 schematic that: CONFIG block of IC2 (FPGA): Various xxx_0 inputs (ie: bank 0) are wired to 3.3V signals CFGBVS_0 is externally pulled up to 3.3V POWER block of IC2 shows VCCO_0 and VCCO_14 wired to 3.3V So my guess is that the settings should be: CONFIG_VOLTAGE: 3.3 CFGBVS (Configuration Bank Voltage Selection): VCC0 (selects high range of I/O voltages) I infer that these are actually fixed requirements of the Cmod A7, and if so, maybe they could be set in the board definition file or the default XDC file? Thoughts? Thanks. Graham
  5. Source for Cmod A7 Stopwatch demo?

    I'm wondering where do we find the source for the Cmod A7 Stopwatch demo? One the demo's page (https://reference.digilentinc.com/cmod_a7/cmod_a7/cmod_a7_stopwatch/start) I can only find links for the bit and bin files. Since this is the only one of the Cmod A7 demos that exercises the pins (as opposed to on-board features), it would be useful to have a known-good demo project to modify. Thanks!
  6. Hi, I am trying to make conventional FT2232H JTAG work with the CMOD A7. The method is standard and has been used for many years (e.g. xc3sprog.exe), my code works with many other boards, including the Digilent-licensed adapters sold by Trenz-Elektronik. My board itself is functional (Vivado Hardware manager recognizes it correctly), but I can't get my own JTAG code to work: The data readback pin of the JTAG interface appears to be stuck on HIGH. Any attempt to read IDCODE, or loop data through BYPASS mode, returns all-ones 0xFF. Unfortunately, there is a missing page in the schematic: The TMS, TCK, TDI_FPGA and TDO_FPGA lines (page 2 quadrant B2) seem to go nowhere. My question: Can you please provide the necessary information to make a "conventional" FTDI JTAG interface work with this board? It would be a very interesting module, but I need my own JTAG ... Maybe I'm missing only some GPIO settings for the remaining pins of the FT2232H bank, but without documentation there isn't much I can do.
  7. CMOD A7 System Generator

    Hi, Can I use a CMOD A7 to run co-simulations using Vivado System Generator? In previous versions of System Generator it was possible to add custom boards. Is there a way to do it in Vivado?
  8. Hi All, I have the Cmod A7 35T, downloaded Vivado 2016.4, and I am on Windows 7 OS. When I go into the hardware manager I can connect to the localhost (connect_hw_server) but when I attempt open_hw_target I get the following error in the Tcl Console: Error: [Labtoolstcl 44-469] There is no hw_target. I've checked to make sure that my device drivers are up to date. I'm just using a standard micro-usb cable that I had in my house. According to Digilent, I don't need a special USB cable. Any help or advice you could provide would be extremely appreciated. Thanks! Edit: I've tried a few more things and want to provide some more information. I've uninstalled and reinstalled Vivado. When I reinstalled it I made sure that "Install Cable Drivers" was selected. I went into Device Manager and made sure my drivers were up to date. There was even an iteration where I uninstalled the drivers and manually installed them from the command line. When I plug in my Cmod A7, the out of box demo is already loaded on the board. I can click button 0 and the LEDs "count" as expected. I have Tera Term and I can click button 2. Tera Term then displays the Memory Test Application as expected.
  9. Program CMod A7 35T without Vivado

    Hi, I have a question, there is a way to programm my Cmod A7 without Vivado->Hardware Manager? I got some issues with Vivado, sometime crash. Another question is, there is a way to separate programming phases? At moment i have a download.bit, firmware.srec and data.txt, with hardware manager i have fused them in firmware.mcs and have flashed it in my SPI Flash. There is a way to program my flash only with download.bit and firmware.srec and later with data without overriding the other memory banks? Kind Regards Stefano
  10. Hi all, I have an interrupt that is generated by a custom ip and when it is triggered, I read a register from the custom ip and read from the pmod sf3 to write those values back to the custom ip. However the interrupt gets stuck and won't return to the main code when I have the pmod sf3 code in there, but it does when I just read a value from the custom ip and print it. I have attached the c code that I have written. Any ideas why this is happening? Thanks! c_code.txt
  11. For bitstream encryption using battery-backed RAM, you are suppose to supply the Vccaux pin with voltage to keep the encryption key alive in memory. 1. Where is the Vccaux pin on the Cmod A7? (Hopefully it is not the VU pin because it would be really wasteful to power the whole FPGA just to keep the encryption key alive!) 2. What voltage is supposed to be supplied? Thanks, David
  12. Programming Flash CMOD A7

    Hi all, I programmed my flash recently, but the sdk .elf file didn't seem to be working so I attempted the whole process again. However, now my board seems to be stuck in somewhere not so good. When I plug the USB in, only a red led is on, compared to originally before flash, the orange done led was also on. Also, now I can no longer program the qspi flash in vivado hardware manager anymore. It always fails during the programming stage because the blank check fails. Is my flash stuck in some kind of mode? Also, how can I clear it and restore my fpga to it's original state? Thanks!
  13. CMOD A7 35t BRAM Problem

    Hi all, I'm trying to read and write to a BRAM on the CMOD a7 35t (artix 7). However, it always reads back zero. I set it up the same way on the ARTY board and it read back fine. Does anyone know the explanation for this, or have any possible solutions? Thanks!
  14. Cmod A7 communication with Arduino

    hi, i have a question. I need to communicate with my Cmod A7 35T using arduino. I know that it is can't communicate directly but i found a middle chip that could be a solution. This component is : http://www.hobbytronics.co.uk/usb-host-serial with new firmware i can set on this chip the right communication port. My design is something like this, arduino send serial data to usb host that convert and send them to cmod, i have setted the right coomunication port and the right boudrate but there is an issues. I can see the datas flow (using the led) but USB-UART bridge can't read it. I set ISR with only one function that take each byte and print it. But nothing is read by uart. i don't know if i have explained the problem, but i ask some information about it. regards Stefano
  15. Hi: I was wondering if anyone has used the MicBlaze - AXI based access to the XADC to communicate with the AUX4 (XSM_CH_AUX4??) and AUX12 (XSM_CH_AUX12??) channels. Based on my read of the XADCdemo.sv and the comments, I guess the CMOD A7 analog inputs to be the XSM_CH_AUX 4 and 12 channels. I seem to be missing something with regards to how to initialize them. Thoughts? Peter
  16. I spotted a question on Stack Exchange's electronics forum regarding symbols in the A7's schematic … http://electronics.stackexchange.com/q/268746/104515 I'm not the original poster, but I'm now very curious too – what do those coloured blocks on certain groups of pins mean?
  17. CMOD A7: get pins toggling first time

    Hello, Newbie here. Trying to get some pins toggling as a first step with my own code. Can anyone suggest what may be wrong my verilog and xdc ? It cant be much more basic than this. Perhaps I havent enable output buffers or something. I am completely new to FPGA but experienced with CPLDs and have a handle on Vivado. btw...it synth, implements, generate bitstream & programs the CMOD A7 ...but I just dont get any external toggling viewed via scope. Thanks. dig1-CmodA7 - forum.xdc digmux1-reduced-forum.v
  18. UART communication control with CMOD A7

    Hi everybody, I have to communicate with the FPGA on my CMOD A7 board through the on board FTDI FT2232HQ chip. While on a PmodUSBUARD, for example, I can use the RTS/CTS hardware wires for the flow control, on the board datasheets it's written that I can only use the TX and RX hardware wires and that there are no RTS/CTS wires (fact confirmed by the board .xdc file too). How can I set reliable control flow for my high-speed communication (from 6Mbaud to 12Mbaud) ? Any advice? Thank you in advance, Antonio Daril Crispino
  19. Hi, I have encountered a problem programming the flash of my CMOD A7 35T with the bootloader image, so that the FPGA would automatically configure itself after power on. Briefly, I placed my project (through its linker script) into the SRAM CELLS of the board and I programmed the flash with the SREC of the project. Now, if I program the FPGA with the bootloader elf (placed into the BRAMs), it works fine (the bootloader actually moves the program data from flash to the SRAM CELLS). But if I try to program the flash with the download.bit (created with "Program Flash" and the bootloader .elf) it doesn't do anything. I followed these guides: - https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start - http://www.xilinx.com/support/answers/64238.html - http://www.xilinx.com/support/answers/63605.html I also created a .mcs file with both the download.bit (FPGA config file) and the project SREC) with this TCL command in Vivado: write_cfgmem -format mcs -size 4 -checksum FF -interface spix4 -loaddata "up 0x0 /path/to/download.bit up 0x00C00000 /path/to/peripheral_test.srec" -force peripheral_test but it didn't work. I really need to write the FPGA config file toghether with the bootloader image to the flash. How can I solve this problem? Thank you in advance, Antonio Daril Crispino
  20. hi, i'm trying to create a simple desing with a microblaze and a custom IpCore with axi stream comunication, but when i try to implement it, Vivado show me the followingmessage : "[Place 30-640] Place Check : This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 53 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device." how i can fix it?
  21. Hi Guys, I am following the instruction from Digilent about the booting MicroBlaze Project with SPI instruction, I got error right after I create the SREC_SPI_Bootloader using templete https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start after step 1.5, I got error: "ddd.elf section `.rodata' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_microblaze_0_local_memory_dlmb_bram_if_cntlr' ddd C/C++ Problem" "region `microblaze_0_local_memory_ilmb_bram_if_cntlr_microblaze_0_local_memory_dlmb_bram_if_cntlr' overflowed by 2864 bytes ddd C/C++ Problem" I know this system only 4Mb Flash, so, the #define FLASH_IMAGE_BASEADDR 0x00300000. But, I even tried to change to FLASH_IMAGE_BASEADDR 0x00000001, system still report me the same error. Here is my system setup: I am using 16K data cache and instruction cache. There is no error with "Hello word" project, I could run with no issue. Did some one have this same issue or any suggestion for this?
  22. XADC Simultaneous Sampling

    Hi,Even though I think this board should be towards questions about Digilent boards specifically, see if you can help me (I tried Xilinx forums without success). I am using the XADC's Vaux4 and Vaux12 on my Cmod A7. However, I'm having difficulties implementing the simultaneous sampling function using the XADC Wizard (Vivado 2016.2). From the wizard I get the ADC module with one address_in "pin" and one data_out "pin". My question is, if it is sampling both pairs simultaneously, how do I access the data? Wouldn't it be necessary to have two data outputs, one for each pair? How does it work? Thank you guys for your time and patience,Leo
  23. Cmod A7 DIP Footprint

    Hi everyone, I want to use the Cmod A7-15T on a custom application and I would like to have the board's DIP footprint. Basically what I want to do is solder a female header to a PCB so I can stick the Cmod A7 into it. If you could provide me with the DIP dimensions that would be highly appreciated. Thanks, Leonardo