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On Cmod A7, the xdc file lists pio to pio, but there are gaps at 15,16 (which are instead analog input pins) and 24,25 (which don't exist). So when I create a Verilog top module that uses pio, how to I specify these discontinuous ranges? Conceptually I want: module top ( input sysclk, output [1:14, 17:23, 26:48] ) but obviously that's not valid syntax. So how DO you use the full set of pio's as written in the xdc file? The file in question: https://raw.githubusercontent.com/Digilent/digilent-xdc/master/Cmod-A7-Master.xdc