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Found 2 results

  1. Hi, I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed. To achevieve this goal, I designed a self made pcore to act as a clock generator. This "720p compliant clock generator" pcore is a simple vhdl/mpd file. Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE. The idea was to replace the original clock generator of the design with this core. Instead of delivering 600Mhz and 75MHz outputs, it del
  2. I am using a Nexys-4 DDR board which has an internal clock of 100 MHz frequency. I am using clocking wizard to generate a pulse of 6.78 MHz and duty ratio of 0.3. I am getting the correct result in simulations but when I observe the output on oscilloscope I do not see a proper pulse. It does not have sharp edges. I get a proper output for lower frequencies. I am unable to find out what is the reason behind this. I am using a 200 MHz bandwidth DSO and an x10 probe for measuring the output. Thanks, Yogita