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Found 25 results


    Cmod A7-35T clock on board question

    Dear All, I bought this board (I'm waiting to receive it) meantime I'm looking the electrical schematic and I've noticed about the clock frequency that IC4 (sheet 3/7 Rev B.1) should be a 100 MHz clock, also I can see a USB_12MHZ line that came into the GCLK line through a resistor R80, I kindly ask you if U4 is the predefinited source of clock of the FPGA and then R80 is not mounted into the board because I need to setup a design able to operate with a 50 MHz clock and if the supplied clock generator supplied with the board is 100 MHz I'm very happy. Could you please let me know more about this point? Thanks! Best regards Grinch
  2. dgottesm

    Using an external clock

    Hi I am using a Zybo Z7-20 to collect video data which comes with its own clock. Meaning that it the video source has 8 parallel bits and a clock with which to sample them. My plan was to make the entire design synchronous to this external clock, but then someone told me that it can be problematic to use an external clock. Can anyone confirm this? I see that there are a lot of different kinds of clocks (bufg,bufio...) Can anyone give advice/tips/useful info on this?
  3. luigee581

    Sampling with Pmod AD1

    Hello! I recently purchased the Pmod AD1 for the Zynq Z7-10 and I am trying to sample at 44.1 kHz. How can I set up a clock in the PL for this? Every time I set up a PL fabric clock to a multiple of 44.1 kHz, it is off by maybe ~500 Hz or more. Thank you in advance.
  4. M. Betz

    CMOD A7: accessing the SPI Flash

    I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz
  5. If anyone remembers J Collins ping pong levitation system ( I'm looking for someone who has replicated it. I want to use it as a vertical clock and was wondering if the fan can be controlled in such a way as to reproducibly achieve the same ball height so that the height can be controlled by a clock in order to assign height to time markings along the tube. Would need ball to indicate time to within +/- 30 minutes. Thanks.
  6. I am looking for an FPGA development board that can generate tunable output-clock from 1MHz to 200MHz with signal swing between 0V and 1.8V. Is there a special one you would recommend? I was looking at "Genesys 2 Kintex-7 FPGA Development Board" - can this produce such clocks with 0V-1.8V swings? Which pins would be configurable for up to 200MHz and 0V-1.8V? Thank you for your help.
  7. spartacus28

    Pmod ALS

    Hi, I am new to this forum so still getting used to things. I am trying to implement the Pmod ALS on an FPGA, and I require to comply with the SPI protocol. I understood the protocol, but the only problem I have is this. "The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on the subsequent rising edge of SCLK, consist of three leading zeroes, the eight bits of information with the MSB first, and four trailing zeroes." As far as I know, 3+8+4=15, and not 16, so where is the extra clock cycle and what is it doing? Is the sensor providing 4 irrelevant numbers before the 8-bit of information and then 4 irrelevant numbers again? Any help will be appreciated. Thanks.
  8. vicvicvar

    Creating a 25 Mhz clock on the Basys 3

    Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I want to call it I just make a instance of this class. In Vivado, when I open my synthesized project and click [Tools ---> Edit devices properties] This is where I select my clock frequency as 50 MHZ { Please see image attached } So my questions are : Is this the proper way to set up a clock using Vivado and the Basys3 Board?In the main page of the Basys3 it says that one can get a clock as high as 450 Mhz but in the options of the [Tools ---> Edit devices properties] I can only find clocks as high as 66 MhzAnd just some basic ones Why Vivado takes sooo long to synthesized, implement and generate the bitstream of an easy and small code? Just implementing in hardware an AND gate takes me 5 minnutes to download the program to the board. Is there a quicker way ? Thanks Forum .
  9. Nystflame

    Arty Microblaze Speed Question

    Hello, Without implementing a timer, I had thought that toggling a GPIO pin and observing the result via a logic analyzer(has 100Megasample/sec). The Microblaze input clock is coming from the "ui_clk" from the MIG, which seems to be 83 MHz, but when observing the pin toggle the frequency is ~37 kHz. My method for toggling the pin is just an infinite while loop with two Xil_Out32 commands, one for turning the pin on, and the other command turns it off. Any debugging methods I should try as to why the frequency of this switching is so low? p.s. I've since moved from toggling via the xil_out function and am targeting the address of the GPIO pins directly, the frequency I'm seeing now is 130.7kHz, still nowhere near the 80MHz I had been expecting. p.s.s. I've enabled caches and tried block ram vs ddr and the max i've gotten to is 1.3Mhz The following is all of the code in my program for this test: #include "platform.h" int main(void) { init_platform(); volatile unsigned int *pins = (volatile unsigned int *) 0x40000000; for(;;){ pins[0] ^= 0x1; } cleanup_platform(); } Best Regards, nystflame
  10. etownsend

    Cmod A7 Clocking

    The schematic diagram for the Cmod A7 shows a clock with part number ASEM1-100.000MHZ-LC-T, which is a 100MHz clock. However when I look at the actual clock component it says it's 12MHz chip, which I confirmed by scoping the output. Is there any way to get a 100MHz clock signal out of this board?
  11. For the past 3 weeks i have been fiddling around a bit with zybo even though i have just found out about what an fpga is using vivado i have made some simple projects like a full adder using vhdl source code and hardware manager, an AXI IP block that can output PWM for given DUTY and Frequency/Period input. But now i have hit a stand still in my new IP design, i need two counters that run simultaneously one will be a clock running at 50Mhz and the other will be catching the input signal the block gets and counting it. My main problem is if i put both counters in the same process are they still as sensitive, and if they are not how can i trigger the other counter without getting a Multi-driven net error when one reaches the limit i want if they aren't in the same process(like one counter counts as a clock and gives me the info about the other clock in 10 ms intervals, in a way an encoder would.)
  12. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blocking statement it would seem that in order to get past that block, there must be some clock checking the incoming value before the logic can continue. Is this true? Or am I missing something. Is there a clock in the fpga that is pushing the logic along? Flymario
  13. wanderso

    Adjusting the clock in the Arty's XDC

    I have the sample constraint file for my Arty board. I notice that where it says a clock signal is created in the file, it specifies a specific port that the clock is found on, specifically PACKAGE_PIN E3. set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; This creates a 100 MHz clock for the Arty. However, my current project needs a 20 MHz clock. I lack the FPGA knowledge to know whether these two lines of code are *describing* a clock that already exists at E3 on the Verilog board, or *creating* it. The "create clock" implies that it's creating, but the way the rest of the constraint file is formatted - with a list of the pins that exist on the Arty and their locations - suggests that it's only describing. Is it safe or even possible to make a 20 MHz clock by simply changing the number after -period to 50.00 for a 50 ns 20 MHz clock? Is there a way I can also keep the 100 MHz clock at the same time?
  14. I'm working with a sensor that uses clock stretching to tell the master when data is ready. When using the AD2 as an I2C master, the analyzer insists there's a NACK after an address somewhere, but I can't see where. The first attached picture shows a write to 0x40, ACK, 0xF1, restart, read from 0x40, ACK, then slave holds both SCL and SDA low. About 68ms later (seen in the second attached picture), the slave releases the bus indicating the data is ready. The protocol analyzer shows the correct sequence from its point of view, then shows "NACK after address" even though all bytes were clearly ACK'd. From what I can tell, I'm using everything correctly. Does WaveForms 2015 actually support I2C clock stretching when acting as an I2C master? As a matter of curiosity, you might be wondering why I chose to use an analog analyzer to view the I2C lines. That's because I can't seem to coerce the logic analyzer to behave while I was also using the protocol analyzer. Is that a software limitation, a bug, or am I just using it wrong?
  15. pamcheese

    CPLD Cool Runner II Clock

    I am trying to implement a simple JTAG chain in a Cool Runner II development board. I am taking various TDI and TDO signals and routing them in the CPLD depending on what FPGAs are powered on. I see that the CMOD CPLD board provides headers for the clock pins but no actual clock. Can I run a design without a clock if it's just simple switches inside the CPLD to interconnecting TDI and TDO signals?
  16. jr2


    Hi, I would like to use a PMOD AMP3 in stand-alone mode via I2S with arduino m0. According to, I understand that by leaving JP2 open, MCLK is generated based on BCLK. However, at page 14 in the datasheet it seems that the work is just the opposite, BCLK could be generated based on MCLK. Is there any chance not to use MCLK in stand-alone mode? or is this signal always needed? Regards.
  17. Hello All, I am trying to acquire a waveform from one of my terminal of the ESP8266 microcontroller (GPIO0). I should be expecting a signal from the crystal at this terminal which is oscillating at 26 MHz. Can anybody let me know the correct settings to acquire the signal of 26 Mhz? The following are the steps that I performed: 1. Go to settings--> Device Manager --> select 2x 16K scope 2. Then click the settings (gear symbol) on the time settings box on the right side of the window 3. Here, I select Range Mode = Division Mode, Rate = 100 MHz, Samples = Default I have attached the snip shots below. The signal intended to measure should be in 26 MHz. It usually says samples lost- reduce the sample rate. Why does it say that? Please let me know the correct settings to measure this signal. The overall objective of measuring the time response on this terminal and maybe the frequency response at this terminal is to figure out which component in my custom board is behaving differently from the other boards which are tested as okay. Please let me know if there is a way to do it using Analog Discovery.
  18. ##Clock signal set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports clk_50] #create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; In this constraints what modifications should I used to get 50MHz clock?
  19. malkauns

    Reading data from MIPI CSI-2 camera sensor

    I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)" "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first." Using VHDL and Vivado, how do I create logic to successfully read data from this sensor? I have the following code written (with notes/questions) but I'm pretty sure its wrong. It was put together based on my limited understanding and reading various other source code that perform similarly: I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value. If it is 1, increment the delay value. This way the delay should always be within +/- 1 of the ideal value. I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute). This is probably due to random chance. Really need help on this one!
  20. Saad Bin Shafique

    Create customized clock using counters

    Hi. I want to generate 15MHz clock from 40MHz system clock. I could use DCM to generate this clock but i want to use counter for that purpose. Can someone tell me that how can i do that?
  21. Juilan Daum

    Missing Oscillator

    Hi, I'm working with the Nexys 4 FPGA, trying to pass the 100 MHz clock from E3 to G1 (Pin JD3), and I'm seeing no output there. When I flip the board over, I noticed X2 is populated (looks like an 8 MHz oscillator), but X1 has no component, and it's the same size and form factor. Is X1 missing something? Thanks for any help!
  22. omikron

    Clocking critical warning

    Hello I am using AXI_dynclk and rgb2dvi from Digilentic git. The ref clock od dynclk core comes to AXI_clk pin. When placing the design, I will always get this critical warning for each generated clock. And the design says Completed but timing constraints not met. How can I fix this?
  23. wheezs

    cmod 6 clock

    hey i cant finger out how to get the internal clock to use in projects
  24. Hi, Does anyone know whether I can replace the crystal oscillator in Max32 with some other oscillators please? I have a 10 MHz master clock, and want to use this clock in the microcontroller. Is it easy to replace the oscillator? Or do I need to unsolder something? Thanks, Jack
  25. How can I set up a variable clock signal on Basys 2?