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  1. In the board description for the ArtyS7, it's written to have a 12 MHz system clock at pin F14. That's not correct. Schematic revision E.1 for ArtyS7 is showing IC2 is open => no clock at all IC2 is - if soldered - a 100 MHz clock => ASEM1-100.000MHZ-LC-T As also discovered by the author of the board description, 12 MHz is a useless clock for 7-series FPGA,s because it's to slow for clock modifying blocks (PLL, MMCM, ...) The trace 12MHz/UCLK has a R0, but no source in schematics (incomplete schematics or an open trace ...) As a summary: the ArtyS7 board has o
  2. I'm learning how to generate clocks with XDC files, using the .xdc from the Basys 3 github repository as a starting point. I'd like to change the clock to a very low frequency of 1 Hz, or once per second, so that a LED blinks on and off once a second. The portion of the .xdc file that generates the clock looks like this: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 1000000000.00 [get_ports clk] And the code for blinking the LED looks like this: module oneclock (
  3. Hello, my name is Caleb. I am a senior electrical engineering student at Northern Illinois University. I am using the Analog Discovery 2 in order to capture analog pixels sent from a sensor at 5MHz and then interpreting that data on the Raspberry Pi 4. I am running into questions with the timing of the logging function of the oscilloscope on the Analog Discovery. I have noticed that when I send multiple acquisitions at once I run into issues with the timing on the next acquisition. It seems that each acquisition comes in order, but there is a delay between the end of one and the beginning
  4. Hi there! I'm trying to make differential clock(100MHz from oscillator) to differential clock output(40MHz differential) clk_100M_P&M is connected to external crystal oscillator(input) and I allocated clk_40_P&M to PIO port(output). clk_front , clk_back is for check point. when I checked, the result was : clk_front : 100MHz & clk_back : 40MHz . However, clk_40_P &N port didn't output some waveform. I have no idea what's the problem. 1st trial : clk_front & back : LVCmos33 and clk_40_P & N : LVDS25 -> result : LVCmos33,(bank34)
  5. Hi , I am using Arty 7 kit to implement my design. At first I used a clock frequency of 130 MHz, and the timing was "met" . Then I increased the clock the clock frequency to 260 MHz , but the timing constraints were "not met" . Pls, see the attached picture. I read about the issue and I found myself I have to do some floorplanning for my design. How to do floorplanning? What is the first step that I have to do with floorplanning ? Thanks.
  6. Regarding the the board Artix-7 (CMOD-A7) - The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.
  7. Dear All, I bought this board (I'm waiting to receive it) meantime I'm looking the electrical schematic and I've noticed about the clock frequency that IC4 (sheet 3/7 Rev B.1) should be a 100 MHz clock, also I can see a USB_12MHZ line that came into the GCLK line through a resistor R80, I kindly ask you if U4 is the predefinited source of clock of the FPGA and then R80 is not mounted into the board because I need to setup a design able to operate with a 50 MHz clock and if the supplied clock generator supplied with the board is 100 MHz I'm very happy. Could you please let me know mor
  8. Hi I am using a Zybo Z7-20 to collect video data which comes with its own clock. Meaning that it the video source has 8 parallel bits and a clock with which to sample them. My plan was to make the entire design synchronous to this external clock, but then someone told me that it can be problematic to use an external clock. Can anyone confirm this? I see that there are a lot of different kinds of clocks (bufg,bufio...) Can anyone give advice/tips/useful info on this?
  9. Hello! I recently purchased the Pmod AD1 for the Zynq Z7-10 and I am trying to sample at 44.1 kHz. How can I set up a clock in the PL for this? Every time I set up a PL fabric clock to a multiple of 44.1 kHz, it is off by maybe ~500 Hz or more. Thank you in advance.
  10. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers
  11. If anyone remembers J Collins ping pong levitation system ( I'm looking for someone who has replicated it. I want to use it as a vertical clock and was wondering if the fan can be controlled in such a way as to reproducibly achieve the same ball height so that the height can be controlled by a clock in order to assign height to time markings along the tube. Would need ball to indicate time to within +/- 30 minutes. Thanks.
  12. I am looking for an FPGA development board that can generate tunable output-clock from 1MHz to 200MHz with signal swing between 0V and 1.8V. Is there a special one you would recommend? I was looking at "Genesys 2 Kintex-7 FPGA Development Board" - can this produce such clocks with 0V-1.8V swings? Which pins would be configurable for up to 200MHz and 0V-1.8V? Thank you for your help.
  13. spartacus28

    Pmod ALS

    Hi, I am new to this forum so still getting used to things. I am trying to implement the Pmod ALS on an FPGA, and I require to comply with the SPI protocol. I understood the protocol, but the only problem I have is this. "The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on the subsequent rising edge of SCLK, consist of
  14. Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I wan
  15. Hello, Without implementing a timer, I had thought that toggling a GPIO pin and observing the result via a logic analyzer(has 100Megasample/sec). The Microblaze input clock is coming from the "ui_clk" from the MIG, which seems to be 83 MHz, but when observing the pin toggle the frequency is ~37 kHz. My method for toggling the pin is just an infinite while loop with two Xil_Out32 commands, one for turning the pin on, and the other command turns it off. Any debugging methods I should try as to why the frequency of this switching is so low? p.s. I've since moved from toggling via
  16. etownsend

    Cmod A7 Clocking

    The schematic diagram for the Cmod A7 shows a clock with part number ASEM1-100.000MHZ-LC-T, which is a 100MHz clock. However when I look at the actual clock component it says it's 12MHz chip, which I confirmed by scoping the output. Is there any way to get a 100MHz clock signal out of this board?
  17. For the past 3 weeks i have been fiddling around a bit with zybo even though i have just found out about what an fpga is using vivado i have made some simple projects like a full adder using vhdl source code and hardware manager, an AXI IP block that can output PWM for given DUTY and Frequency/Period input. But now i have hit a stand still in my new IP design, i need two counters that run simultaneously one will be a clock running at 50Mhz and the other will be catching the input signal the block gets and counting it. My main problem is if i put both counters in the same process are they
  18. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blo
  19. I have the sample constraint file for my Arty board. I notice that where it says a clock signal is created in the file, it specifies a specific port that the clock is found on, specifically PACKAGE_PIN E3. set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; This creates a 100 MHz clock for the Arty. However, my current project needs a 20 MHz clock. I lack the FPGA knowledge to know whether these two lines of code are
  20. I'm working with a sensor that uses clock stretching to tell the master when data is ready. When using the AD2 as an I2C master, the analyzer insists there's a NACK after an address somewhere, but I can't see where. The first attached picture shows a write to 0x40, ACK, 0xF1, restart, read from 0x40, ACK, then slave holds both SCL and SDA low. About 68ms later (seen in the second attached picture), the slave releases the bus indicating the data is ready. The protocol analyzer shows the correct sequence from its point of view, then shows "NACK after address" even though all bytes were clea
  21. I am trying to implement a simple JTAG chain in a Cool Runner II development board. I am taking various TDI and TDO signals and routing them in the CPLD depending on what FPGAs are powered on. I see that the CMOD CPLD board provides headers for the clock pins but no actual clock. Can I run a design without a clock if it's just simple switches inside the CPLD to interconnecting TDI and TDO signals?
  22. jr2


    Hi, I would like to use a PMOD AMP3 in stand-alone mode via I2S with arduino m0. According to, I understand that by leaving JP2 open, MCLK is generated based on BCLK. However, at page 14 in the datasheet it seems that the work is just the opposite, BCLK could be generated based on MCLK. Is there any chance not to use MCLK in stand-alone mode? or is this signal always needed? Regards.
  23. Hello All, I am trying to acquire a waveform from one of my terminal of the ESP8266 microcontroller (GPIO0). I should be expecting a signal from the crystal at this terminal which is oscillating at 26 MHz. Can anybody let me know the correct settings to acquire the signal of 26 Mhz? The following are the steps that I performed: 1. Go to settings--> Device Manager --> select 2x 16K scope 2. Then click the settings (gear symbol) on the time settings box on the right side of the window 3. Here, I select Range Mode = Division Mode, Rate = 100 MHz, Samples = Default I ha
  24. ##Clock signal set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports clk_50] #create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; In this constraints what modifications should I used to get 50MHz clock?
  25. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter i