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Showing results for tags 'clock frequency'.
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Hi everyone, I've been reading Xilinx's DS643 pdf on MPMC configuration (v6.06.a). Table 91 page 170 lists the maximum frequency that can be used for the VFBC interface clocks, VFBC_Cmd_Clk, VFBC_Wd_Clk and VFBC_Rd_Clk. Only Spartan-3A DSP, Virtex-4 and Virtex-5 devices are listed. Where can I find the maximum frequency that can be used to clock VFBC on Atlys spartan-6 ? Thanx a lot, cheers.
Hi all, I am going to order a FPGA development board. So far I am considering Anvyl Spartan-6. I mainly use it to generate some pulse at the sequence at the time interval of 2ns or lower. I found that Spartan-6 has the frequency of about 500MHz, but is that just the maximum frequency that I may have? After considering all other elements in the board, the actual frequency will be lower than that? The second question on that board is if that support labview programming? Can I control the FPGA directly from labview platform? Thanks.
I am using the Nexys 3 board alongside the PmodI2S - Stereo Audio Output. After reading the data sheet for this PMOD, http://www.cirrus.com/en/pubs/proDatasheet/CS4344-45-48_F2.pdf (see Table 1 on pg.12) it seems as though I have to create an abnormal clock frequency. And by abnormal I mean a clock that cannot be created using a clock divider. For example, table 1 in the data sheet suggests that I use a master clock of 22.5792MHz, but there is no such whole number (call it X) where the Nexys system clock: 100MHz/X = 22.5792MHz. So, what are my options?