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  1. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and source verilog is attatched. Thanks. I also put this on the xilinx forums but accidently posted it in the wrong catagory, so I will put it here too. `timescale 1ns / 1ps module tb; // this testbench from timing diagram memory uage guide. wire [15:0] DO; reg [10:0] ADDR; reg CLK; reg [15:0] DI; reg EN; reg REGCE; reg RST; reg [1:0] WE; always #4 CLK = ~CLK; BRAM_SP_2048x16 uut(DO,ADDR,CLK,DI,EN,REGCE,RST,WE); initial begin CLK = 0; DI = 16'hDDDD; ADDR = 11'h000; EN = 0; REGCE = 0; RST = 0; WE = 2'b00; #1 EN = 1; #8 DI = 16'hCCCC; ADDR = 11'h00F; WE = 2'b11; #8 ADDR = 11'h07E; DI = 16'hBBBB; WE = 2'b11; #8 ADDR = 11'h08F; DI = 16'hAAAA; RST = 1; WE = 2'b00; #8 ADDR = 11'h020; DI = 16'h0000; RST = 0; EN = 0; #4 $finish; end endmodule 7_series_BRAM_SP.v