Search the Community

Showing results for tags 'cfgbvs'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. Hi folks, I'm using some very basic examples with Cmod A7, which work in the sense that they result in a behaving FPGA. However, I'm trying to get rid of, or at, least understand the various warnings. One warning that occurs for all examples I tried is: CFGBVS-1#1 Warning Missing CFGBVS and CONFIG_VOLTAGE Design Properties Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: ... OK, I see where to set them in the Tools > Edit Device Properties window, but I'm not sure what to set them to for the Cmod A7. Available values are: CONFIG_VOLTAGE: 1.5, 1.8, 2.5, 3.3 CFGBVS (Configuration Bank Voltage Selection): GND, VCC0 ... but I'm not too inclined to just experiment with different values, for fear of doing some damage. (Though somehow, the default blank settings appear to work, other than the warning message.) Questions: Do these settings set something in the FPGA configuration, or do they merely inform Vivado of the hardware's design? Does the specific wiring of this board impose/require only certain values for these items, or can alternatives be chosen? What is/are those settings, and under what circumstances do you use them? This appears to relate: https://www.xilinx.com/support/answers/57045.html. Also ug470_7series_Config.pdf, "Configuration Banks Voltage Select" section. I note on the Cmod A7 schematic that: CONFIG block of IC2 (FPGA): Various xxx_0 inputs (ie: bank 0) are wired to 3.3V signals CFGBVS_0 is externally pulled up to 3.3V POWER block of IC2 shows VCCO_0 and VCCO_14 wired to 3.3V So my guess is that the settings should be: CONFIG_VOLTAGE: 3.3 CFGBVS (Configuration Bank Voltage Selection): VCC0 (selects high range of I/O voltages) I infer that these are actually fixed requirements of the Cmod A7, and if so, maybe they could be set in the board definition file or the default XDC file? Thoughts? Thanks. Graham
  2. Hi everyone, I have a Nexys4 board and I am trying to generate a simple program in VHDL using Vivado 2014.4 Webpack. When I get to the Generate Bitstream phase I get the following warning: ----------------------------- WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 ----------------------- The program apparently works OK even though there is this warning. I am using the constraints file provided by DIGILENT: http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,1184&Prod=NEXYS4 where I have uncommented the clock signal, the 7 segment displays and the first switch. I have tried to solve this but I am new to FPGAs and there is an overwhelming amount of documentation. It would be great if someone could help me. I don't want to change anything and risk damage to the board. I see that the example project provided by Digilent also has the same warnings. Thanks in advance Andres