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Found 18 results

  1. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and sour
  2. Hi everyone, I am currently working with a Zybo Z7010 board on Vivado 2018.3 and am trying to implement a memory access in both reading and writing modes. More precisely, I'd like to enable the user to enter a number of coordinates that define a random waveform (sine table...) and to store it somewhere so that the PL can access it in reading mode and display it through a DAC. Please note that it is essential that the reading process is fast for further applications. Now, have been reading many things but I'm a little confused about the "different types of memories that exist". I
  3. Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display
  4. Hello @jpeyron, Hello others, Kindly, could you check my design ? I want to know am I right or wrong ? could you tell me any suggestions in case I am wrong ? Thanks in advance.
  5. Hi everyone, I'm working on a project in which I've to store data that've been read from SD card into the BRAM in SDK (PS). and read that data from PL in Vivado. The question is how should I connect the BRAM Generator IP with the ZYNQ7 PS IP to give the BRAM access in PS.
  6. Hello! I have an example design where I am writing values into a BRAM. I have confirmed through simulation that the values are stored correctly. However, what I want to do is to confirm that the values are saved running on hardware as well? I have been trying to debug using the TCF debugger and trying to check the Memory window on the uB but I am not getting anything sufficient or understandable. What should I do if I want to, for example, test my memory through the MicroBlaze, shall the D-cache and I-cache be enabled? Could you giv
  7. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  8. I want to store the image matrix into block RAM.In my UART receiver code I have instantiated BRAM module for writing purpose.Is this way is correct? Wheneve Instantiate there is not declring error.Where can I ear functionality of Block RAM
  9. vc26

    CMOD A7 35t BRAM Problem

    Hi all, I'm trying to read and write to a BRAM on the CMOD a7 35t (artix 7). However, it always reads back zero. I set it up the same way on the ARTY board and it read back fine. Does anyone know the explanation for this, or have any possible solutions? Thanks!
  10. vc26

    VHDL read from BRAM

    Hi, I have a block design with a microblaze, a BRAM, and a custom ip (VHDL). With the custom IP, I have 4 separate signals that will read at the same time from 4 consecutive rows in the bram and output the values. I'm having trouble figuring out how to read 4 separate signals from a single BRAM at the same time. Any advice is much appreciated. Thanks, Vic
  11. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,
  12. Hi, The data width of BRAM is 32-bit,if I transfer data to BRAM in SDK,can I use the function Xil_Out8 or should Xil_Out32 ? Regards, Sophia
  13. Hi, I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'. In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition, The interface of BRAM is blk_mem_gen_0 uut( .clka(clka), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clkb), .web(web), .dinb(), .addrb(addrb), .doutb(doutb) ); for address and data, #0 wea=1; web=0; addra=0; dina=0; #10000 addra=1; dina=
  14. I'm working with a Kintex-7 board. Currently my application relies on external DDR, but I want to turn it entirely off internal memory on the FPGA. From what I have gathered online, this is possible to do, but haven't been able to find a clear answer on how to do this with the modern SDK. I can change my linker script to allocate more memory to BRAM and the program will compile. But I"m having trouble in Vivado when trying to generate required hardware with enough memory. I have Microblaze with the following ports: DLMB (data mem) <---> LMB <----> LMB BRAM Control
  15. hi, i'm trying to create a simple desing with a microblaze and a custom IpCore with axi stream comunication, but when i try to implement it, Vivado show me the followingmessage : "[Place 30-640] Place Check : This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 53 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device." how i can fi
  16. I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly. However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole proj
  17. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file
  18. Hello, I'm trying to get to work on my Atlys board but I'm running into errors in SDK. After I clean & build, the elfcheck passes: 10:39:52 **** Incremental Build of configuration Debug for project Atlys_Webserver_Demo **** make all 'Building file: ../src/additional_sf_ops.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunc