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Found 16 results

  1. khaledismail

    Display image using VGA from block RAM

    Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display the image. summary of code functionality: Divide main 100 MHz clock by four to get 25 MHz clock (required pixel frequency) , establish VGA synchronization and display the image on a 640 x 480 resolution @ 60 Hz. The code is shown below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity vga_driver is Port ( clk : in STD_LOGIC; --100 MHz main clock. Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; R,G,B : out STD_LOGIC_VECTOR (3 downto 0)); end vga_driver; architecture Behavioral of vga_driver is signal DFlipFlopOut1: STD_LOGIC; signal DFlipFlopOut1_NOT: STD_LOGIC; signal ClockDiv4: STD_LOGIC; -- 25 MHz Clock signal ClockDiv4_NOT: STD_LOGIC; constant picture_size : Integer:=90000; -- 300 Pixels* 300 Pixels picture= 90000 Pixels --Signals for Block RAM signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0):="0"; signal addra : STD_LOGIC_VECTOR(16 DOWNTO 0):=(others=>'0'); signal dina : STD_LOGIC_VECTOR(11 DOWNTO 0):=(others=>'0'); signal douta : STD_LOGIC_VECTOR(11 DOWNTO 0):=(others=>'0'); constant HD : integer := 639; -- 639 Horizontal Display (640) constant HFP : integer := 16; -- 16 Right border (front porch) constant HSP : integer := 96; -- 96 Sync pulse (Retrace) constant HBP : integer := 48; -- 48 Left boarder (back porch) constant VD : integer := 479; -- 479 Vertical Display (480) constant VFP : integer := 10; -- 10 Right border (front porch) constant VSP : integer := 2; -- 2 Sync pulse (Retrace) constant VBP : integer := 33; -- 33 Left boarder (back porch) signal hPos : integer := 0; signal vPos : integer := 0; signal videoOn : std_logic := '0'; component RisingEdge_DFlipFlop is port( Q : out std_logic; Clk :in std_logic; D :in std_logic ); end component ; component Picture_Block_RAM is PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); end component; begin DFlipFlopOut1_NOT<=not DFlipFlopOut1; ClockDiv4_NOT<= not ClockDiv4; --Pass Main 100 MHz clock to 2 cascaded DFlipFLops to divide frequency by 4. Result frequency= 25 MHz. U1: RisingEdge_DFlipFlop Port map (clk=> clk, D=> DFlipFlopOut1_NOT, Q=>DFlipFlopOut1); U2: RisingEdge_DFlipFlop Port map (clk=> DFlipFlopOut1, D=> ClockDiv4_NOT, Q=>ClockDiv4); --Block RAM containing picture U3: Picture_Block_RAM Port map (clka=>ClockDiv4, wea=>wea, addra=>addra, dina=>dina, douta=>douta); Horizontal_position_counter:process(ClockDiv4) begin if(ClockDiv4'event and ClockDiv4 = '1')then if (hPos = (HD + HFP + HSP + HBP)) then hPos <= 0; else hPos <= hPos + 1; end if; end if; end process; Vertical_position_counter:process(ClockDiv4, hPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(hPos = (HD + HFP + HSP + HBP))then if (vPos = (VD + VFP + VSP + VBP)) then vPos <= 0; else vPos <= vPos + 1; end if; end if; end if; end process; Horizontal_Synchronisation:process(ClockDiv4, hPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if((hPos <= (HD + HFP)) OR (hPos > HD + HFP + HSP))then HSYNC <= '1'; else HSYNC <= '0'; end if; end if; end process; Vertical_Synchronisation:process(ClockDiv4, vPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if((vPos <= (VD + VFP)) OR (vPos > VD + VFP + VSP))then VSYNC <= '1'; else VSYNC <= '0'; end if; end if; end process; video_on:process(ClockDiv4, hPos, vPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(hPos <= HD and vPos <= VD)then videoOn <= '1'; else videoOn <= '0'; end if; end if; end process; draw:process(ClockDiv4, hPos, vPos, videoOn) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(videoOn = '1')then if (unsigned(addra)<picture_size) then R<=douta(11 downto 8); G<=douta(7 downto 4); B<=douta(3 downto 0); addra<=STD_LOGIC_VECTOR(unsigned(addra)+1); else R<=(others=>'0');G<=(others=>'0');B<=(others=>'0'); end if; else R<=(others=>'0');G<=(others=>'0');B<=(others=>'0'); addra<=(others=>'0'); end if; end if; end process; end Behavioral; My problem is that the image does not display as expected. I get this displayed on my screen: As you see, there are 2 problems immediately noticed. 1st: The image is not the same, obviously. 2nd: The image should not take the whole display since it is 300 * 300 pixels while the resolution is 640*480 pixels meaning that some data is being repeated without intention. The default display of BASYS 3 is this. I am putting this just for reference so you can know how my screen displays 640*480 resolution: I tested the VHDL code by printing colors on my screen by direct output assignment and it works as intended. So the problem is probably with accessing the block RAM. A snippet from my .coe file: MEMORY_INITIALIZATION_RADIX=2; MEMORY_INITIALIZATION_VECTOR= 011101010100, 010101110111, 000110011111, 010110101100, 000110111111, 001000100010, 001000100010, 001000100010, 001000100011, 000101100100, 100110100001, 111011010110, 111110110110, 111110000101, 111110010100, : : --it goes on and on until last line, line number 90002, 90000 since 300*300 pixels= 90000. The added two is due to the first 2 lines. : : 101100100010; I am stuck at this point. Where could the problem be?
  2. Ahmed Alfadhel

    I need to use RAM

    Hello @jpeyron, Hello others, Kindly, could you check my design ? I want to know am I right or wrong ? could you tell me any suggestions in case I am wrong ? Thanks in advance.
  3. Hi everyone, I'm working on a project in which I've to store data that've been read from SD card into the BRAM in SDK (PS). and read that data from PL in Vivado. The question is how should I connect the BRAM Generator IP with the ZYNQ7 PS IP to give the BRAM access in PS.
  4. Hello! I have an example design where I am writing values into a BRAM. I have confirmed through simulation that the values are stored correctly. However, what I want to do is to confirm that the values are saved running on hardware as well? I have been trying to debug using the TCF debugger and trying to check the Memory window on the uB but I am not getting anything sufficient or understandable. What should I do if I want to, for example, test my memory through the MicroBlaze, shall the D-cache and I-cache be enabled? Could you give me any suggestions or examples on how to confirm the content without using simulation? My initial goal is to start with a BRAM and then go on with an SDRAM as well. regards John
  5. Notarobot

    What is the fastest way to save PL data

    Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  6. I want to store the image matrix into block RAM.In my UART receiver code I have instantiated BRAM module for writing purpose.Is this way is correct? Wheneve Instantiate there is not declring error.Where can I ear functionality of Block RAM
  7. vc26

    CMOD A7 35t BRAM Problem

    Hi all, I'm trying to read and write to a BRAM on the CMOD a7 35t (artix 7). However, it always reads back zero. I set it up the same way on the ARTY board and it read back fine. Does anyone know the explanation for this, or have any possible solutions? Thanks!
  8. vc26

    VHDL read from BRAM

    Hi, I have a block design with a microblaze, a BRAM, and a custom ip (VHDL). With the custom IP, I have 4 separate signals that will read at the same time from 4 consecutive rows in the bram and output the values. I'm having trouble figuring out how to read 4 separate signals from a single BRAM at the same time. Any advice is much appreciated. Thanks, Vic
  9. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,
  10. Sophia_123

    access to BRAM

    Hi, The data width of BRAM is 32-bit,if I transfer data to BRAM in SDK,can I use the function Xil_Out8 or should Xil_Out32 ? Regards, Sophia
  11. Sophia_123

    Failed to simulate the BRAM test

    Hi, I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'. In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition, The interface of BRAM is blk_mem_gen_0 uut( .clka(clka), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clkb), .web(web), .dinb(), .addrb(addrb), .doutb(doutb) ); for address and data, #0 wea=1; web=0; addra=0; dina=0; #10000 addra=1; dina=2; #100 addrb=0; #1000 addrb=1; #30000 $stop; In simulate wave,dout is always x. What makes it? Regards, Sophia
  12. shubhamgandhi

    Expanding BRAM for a Microblaze application

    I'm working with a Kintex-7 board. Currently my application relies on external DDR, but I want to turn it entirely off internal memory on the FPGA. From what I have gathered online, this is possible to do, but haven't been able to find a clear answer on how to do this with the modern SDK. I can change my linker script to allocate more memory to BRAM and the program will compile. But I"m having trouble in Vivado when trying to generate required hardware with enough memory. I have Microblaze with the following ports: DLMB (data mem) <---> LMB <----> LMB BRAM Controller1 <---> Block memory gen 1 ILMB (instr mem) <-----> LMB <----> LMB BRAM Controller2 <---> Block memory gen 1 AXI_DC (data cache) <-----> External DDR AXI_IC (instr cache) <------> External DDR I want get rid of the external DDR from the design, but the program is too large to sit in the default BRAM allocated size of 32k x 32b wide. Seems like this is hard limit for one block, but it is possible to cascade more to expand the depth. I have verified that there is way more than enough total BRAM in the FPGA to store the program. In Vivado, Has anyone be able to do this or knows how it can be done?
  13. hi, i'm trying to create a simple desing with a microblaze and a custom IpCore with axi stream comunication, but when i try to implement it, Vivado show me the followingmessage : "[Place 30-640] Place Check : This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 53 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device." how i can fix it?
  14. ntrstd11

    Modifying BRAM initial value quickly

    I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly. However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.
  15. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?
  16. evanrichter

    Getting Atlys Webserver Demo to Work

    Hello, I'm trying to get http://www.digilentinc.com/Data/Products/ATLYS/Atlys_AXI_Web_Server_Demo_v_1_02.zip to work on my Atlys board but I'm running into errors in SDK. After I clean & build, the elfcheck passes: 10:39:52 **** Incremental Build of configuration Debug for project Atlys_Webserver_Demo **** make all 'Building file: ../src/additional_sf_ops.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/additional_sf_ops.d" -MT"src/additional_sf_ops.d" -o "src/additional_sf_ops.o" "../src/additional_sf_ops.c" ../src/additional_sf_ops.c: In function 'hchartoi': ../src/additional_sf_ops.c:837:5: warning: array subscript has type 'char' [-Wchar-subscripts] ../src/additional_sf_ops.c:843:5: warning: array subscript has type 'char' [-Wchar-subscripts] 'Finished building: ../src/additional_sf_ops.c' ' ' 'Building file: ../src/dispatch.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/dispatch.d" -MT"src/dispatch.d" -o "src/dispatch.o" "../src/dispatch.c" ../src/dispatch.c: In function 'print_headers': ../src/dispatch.c:31:9: warning: implicit declaration of function 'print_echo_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:34:9: warning: implicit declaration of function 'print_rxperf_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:37:9: warning: implicit declaration of function 'print_txperf_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:40:9: warning: implicit declaration of function 'print_tftp_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:43:9: warning: implicit declaration of function 'print_web_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c: In function 'start_applications': ../src/dispatch.c:52:9: warning: implicit declaration of function 'start_echo_application' [-Wimplicit-function-declaration] ../src/dispatch.c:55:9: warning: implicit declaration of function 'start_rxperf_application' [-Wimplicit-function-declaration] ../src/dispatch.c:58:9: warning: implicit declaration of function 'start_txperf_application' [-Wimplicit-function-declaration] ../src/dispatch.c:61:9: warning: implicit declaration of function 'start_tftp_application' [-Wimplicit-function-declaration] ../src/dispatch.c:64:9: warning: implicit declaration of function 'start_web_application' [-Wimplicit-function-declaration] ../src/dispatch.c: In function 'transfer_data': ../src/dispatch.c:71:9: warning: implicit declaration of function 'transfer_echo_data' [-Wimplicit-function-declaration] ../src/dispatch.c:74:9: warning: implicit declaration of function 'transfer_rxperf_data' [-Wimplicit-function-declaration] ../src/dispatch.c:77:9: warning: implicit declaration of function 'transfer_txperf_data' [-Wimplicit-function-declaration] ../src/dispatch.c:80:9: warning: implicit declaration of function 'transfer_tftp_data' [-Wimplicit-function-declaration] ../src/dispatch.c:83:9: warning: implicit declaration of function 'transfer_web_data' [-Wimplicit-function-declaration] ../src/dispatch.c:84:1: warning: control reaches end of non-void function [-Wreturn-type] ../src/dispatch.c: In function 'start_applications': ../src/dispatch.c:65:1: warning: control reaches end of non-void function [-Wreturn-type] 'Finished building: ../src/dispatch.c' ' ' 'Building file: ../src/echo.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/echo.d" -MT"src/echo.d" -o "src/echo.o" "../src/echo.c" 'Finished building: ../src/echo.c' ' ' 'Building file: ../src/http_response.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/http_response.d" -MT"src/http_response.d" -o "src/http_response.o" "../src/http_response.c" ../src/http_response.c: In function 'do_delete_file': ../src/http_response.c:529:12: warning: unused variable 'fd' [-Wunused-variable] ../src/http_response.c: In function 'do_list_file': ../src/http_response.c:729:4: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/http_response.c: In function 'do_http_get': ../src/http_response.c:868:4: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/http_response.c: In function 'data_receive_callback': ../src/http_response.c:353:5: warning: 'pcb' may be used uninitialized in this function [-Wuninitialized] ../src/http_response.c: In function 'do_download_file': ../src/http_response.c:459:7: warning: 'buf' may be used uninitialized in this function [-Wuninitialized] 'Finished building: ../src/http_response.c' ' ' 'Building file: ../src/main.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.d" -o "src/main.o" "../src/main.c" ../src/main.c: In function 'main': ../src/main.c:85:2: warning: implicit declaration of function 'lwip_init' [-Wimplicit-function-declaration] ../src/main.c:96:2: warning: implicit declaration of function 'platform_enable_interrupts' [-Wimplicit-function-declaration] ../src/main.c:116:3: warning: implicit declaration of function 'get_switch_state' [-Wimplicit-function-declaration] ../src/main.c:117:3: warning: implicit declaration of function 'get_pushbutton_state' [-Wimplicit-function-declaration] 'Finished building: ../src/main.c' ' ' 'Building file: ../src/platform.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.d" -o "src/platform.o" "../src/platform.c" ../src/platform.c: In function 'timer_callback': ../src/platform.c:50:2: warning: implicit declaration of function 'tcp_fasttmr' [-Wimplicit-function-declaration] ../src/platform.c:54:3: warning: implicit declaration of function 'tcp_slowtmr' [-Wimplicit-function-declaration] ../src/platform.c: In function 'xadapter_timer_handler': ../src/platform.c:62:11: warning: unused variable 'tcsr' [-Wunused-variable] ../src/platform.c:61:12: warning: unused variable 'timer_base' [-Wunused-variable] ../src/platform.c: In function 'init_platform': ../src/platform.c:257:2: warning: implicit declaration of function 'platform_init_fs' [-Wimplicit-function-declaration] 'Finished building: ../src/platform.c' ' ' 'Building file: ../src/platform_fs.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform_fs.d" -MT"src/platform_fs.d" -o "src/platform_fs.o" "../src/platform_fs.c" 'Finished building: ../src/platform_fs.c' ' ' 'Building file: ../src/platform_gpio.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform_gpio.d" -MT"src/platform_gpio.d" -o "src/platform_gpio.o" "../src/platform_gpio.c" 'Finished building: ../src/platform_gpio.c' ' ' 'Building file: ../src/prot_malloc.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/prot_malloc.d" -MT"src/prot_malloc.d" -o "src/prot_malloc.o" "../src/prot_malloc.c" ../src/prot_malloc.c: In function 'prot_mem_free': ../src/prot_malloc.c:39:1: warning: control reaches end of non-void function [-Wreturn-type] 'Finished building: ../src/prot_malloc.c' ' ' 'Building file: ../src/rxperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/rxperf.d" -MT"src/rxperf.d" -o "src/rxperf.o" "../src/rxperf.c" 'Finished building: ../src/rxperf.c' ' ' 'Building file: ../src/tftpserver.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/tftpserver.d" -MT"src/tftpserver.d" -o "src/tftpserver.o" "../src/tftpserver.c" ../src/tftpserver.c:57:8: warning: type defaults to 'int' in declaration of 'tftp_server_started' [-Wimplicit-int] ../src/tftpserver.c: In function 'tftp_process_read': ../src/tftpserver.c:191:13: warning: unused variable 'block' [-Wunused-variable] ../src/tftpserver.c:191:10: warning: unused variable 'n' [-Wunused-variable] ../src/tftpserver.c: In function 'tftp_process_write': ../src/tftpserver.c:276:13: warning: unused variable 'block' [-Wunused-variable] ../src/tftpserver.c:276:10: warning: unused variable 'n' [-Wunused-variable] ../src/tftpserver.c: In function 'start_tftp_application': ../src/tftpserver.c:406:1: warning: control reaches end of non-void function [-Wreturn-type] 'Finished building: ../src/tftpserver.c' ' ' 'Building file: ../src/tftputils.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/tftputils.d" -MT"src/tftputils.d" -o "src/tftputils.o" "../src/tftputils.c" 'Finished building: ../src/tftputils.c' ' ' 'Building file: ../src/txperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/txperf.d" -MT"src/txperf.d" -o "src/txperf.o" "../src/txperf.c" 'Finished building: ../src/txperf.c' ' ' 'Building file: ../src/urxperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/urxperf.d" -MT"src/urxperf.d" -o "src/urxperf.o" "../src/urxperf.c" 'Finished building: ../src/urxperf.c' ' ' 'Building file: ../src/utxperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/utxperf.d" -MT"src/utxperf.d" -o "src/utxperf.o" "../src/utxperf.c" ../src/utxperf.c: In function 'transfer_utxperf_data': ../src/utxperf.c:37:6: warning: unused variable 'copy' [-Wunused-variable] 'Finished building: ../src/utxperf.c' ' ' 'Building file: ../src/web_utils.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/web_utils.d" -MT"src/web_utils.d" -o "src/web_utils.o" "../src/web_utils.c" 'Finished building: ../src/web_utils.c' ' ' 'Building file: ../src/webserver.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/webserver.d" -MT"src/webserver.d" -o "src/webserver.o" "../src/webserver.c" ../src/webserver.c: In function 'http_sent_callback': ../src/webserver.c:86:13: warning: implicit declaration of function 'mfs_file_read' [-Wimplicit-function-declaration] ../src/webserver.c:91:17: warning: implicit declaration of function 'mfs_file_close' [-Wimplicit-function-declaration] ../src/webserver.c: In function 'http_recv_callback': ../src/webserver.c:115:3: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/webserver.c:117:3: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/webserver.c: In function 'start_web_application': ../src/webserver.c:158:2: warning: implicit declaration of function 'platform_init_gpios' [-Wimplicit-function-declaration] 'Finished building: ../src/webserver.c' ' ' 'Building file: ../src/xquad_spi.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/xquad_spi.d" -MT"src/xquad_spi.d" -o "src/xquad_spi.o" "../src/xquad_spi.c" 'Finished building: ../src/xquad_spi.c' ' ' 'Building target: Atlys_Webserver_Demo.elf' 'Invoking: MicroBlaze gcc linker' mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../standalone_bsp_0/microblaze_0/lib -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "Atlys_Webserver_Demo.elf" ./src/additional_sf_ops.o ./src/dispatch.o ./src/echo.o ./src/http_response.o ./src/main.o ./src/platform.o ./src/platform_fs.o ./src/platform_gpio.o ./src/prot_malloc.o ./src/rxperf.o ./src/tftpserver.o ./src/tftputils.o ./src/txperf.o ./src/urxperf.o ./src/utxperf.o ./src/web_utils.o ./src/webserver.o ./src/xquad_spi.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group 'Finished building target: Atlys_Webserver_Demo.elf' ' ' 'Invoking: MicroBlaze Print Size' mb-size Atlys_Webserver_Demo.elf |tee "Atlys_Webserver_Demo.elf.size" text data bss dec hex filename 172996 1552 34190284 34364832 20c5da0 Atlys_Webserver_Demo.elf 'Finished building: Atlys_Webserver_Demo.elf.size' ' ' 'Invoking: Xilinx ELF Check' elfcheck Atlys_Webserver_Demo.elf -hw ../../hw_platform/system.xml -pe microblaze_0 |tee "Atlys_Webserver_Demo.elf.elfcheck" elfcheck Xilinx EDK 14.7 Build EDK_P.20131013 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Command Line: elfcheck -hw ../../hw_platform/system.xml -pe microblaze_0 Atlys_Webserver_Demo.elf ELF file : Atlys_Webserver_Demo.elf elfcheck passed. 'Finished building: Atlys_Webserver_Demo.elf.elfcheck' ' ' 10:40:03 Build Finished (took 11s.626ms) However when I click program FPGA, I get elfcheck -hw C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/hw_platform/system.xml -mode bootload -mem BRAM -pe microblaze_0 C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/Atlys_Webserver_Demo/Debug/Atlys_Webserver_Demo.elf elfcheck Xilinx EDK 14.7 Build EDK_P.20131013 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Command Line: elfcheck -hw C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/hw_platform/system.xml -mode bootload -mem BRAM -pe microblaze_0 C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/Atlys_Webserver_Demo/D ebug/Atlys_Webserver_Demo.elf ELF file : C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/Atlys_Webserver_Demo/D ebug/Atlys_Webserver_Demo.elf ERROR:EDK:3165 - elfcheck failed! The following sections did not fit into Processor BRAM memory: Section .data (0xC002A3D0 - 0xC002A9CF) Section .rodata (0xC0027D04 - 0xC002A3CB) Section .dtors (0xC0027CFC - 0xC0027D03) Section .ctors (0xC0027CF4 - 0xC0027CFB) Section .fini (0xC0027CD4 - 0xC0027CF3) Section .init (0xC0027C98 - 0xC0027CD3) Section .text (0xC0000000 - 0xC0027C97) Try using the linker script generation tools to generate an ELF that maps correctly to your hardware design. Programming the FPGA failed due to errors from elfcheck My lscript.ld file is as follows: /*******************************************************************/ /* */ /* This file is automatically generated by linker script generator.*/ /* */ /* Version: Xilinx EDK 14.3 EDK_P.40xd */ /* */ /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ /* */ /* Description : MicroBlaze Linker Script */ /* */ /*******************************************************************/ _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000000; _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; /* Define Memories in the system */ MEMORY { microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00007FB0 mcb_ddr2_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000 } /* Specify the default entry point to the program */ ENTRY(_start) /* Define the sections, and where they are mapped in memory */ SECTIONS { .vectors.reset 0x00000000 : { *(.vectors.reset) } .vectors.sw_exception 0x00000008 : { *(.vectors.sw_exception) } .vectors.interrupt 0x00000010 : { *(.vectors.interrupt) } .vectors.hw_exception 0x00000020 : { *(.vectors.hw_exception) } .text : { *(.text) *(.text.*) *(.gnu.linkonce.t.*) } > mcb_ddr2_S0_AXI_BASEADDR .init : { KEEP (*(.init)) } > mcb_ddr2_S0_AXI_BASEADDR .fini : { KEEP (*(.fini)) } > mcb_ddr2_S0_AXI_BASEADDR .ctors : { __CTOR_LIST__ = .; ___CTORS_LIST___ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) __CTOR_END__ = .; ___CTORS_END___ = .; } > mcb_ddr2_S0_AXI_BASEADDR .dtors : { __DTOR_LIST__ = .; ___DTORS_LIST___ = .; KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) PROVIDE(__DTOR_END__ = .); PROVIDE(___DTORS_END___ = .); } > mcb_ddr2_S0_AXI_BASEADDR .rodata : { __rodata_start = .; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) __rodata_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .sdata2 : { . = ALIGN(8); __sdata2_start = .; *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) . = ALIGN(8); __sdata2_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .sbss2 : { __sbss2_start = .; *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) __sbss2_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .data : { . = ALIGN(4); __data_start = .; *(.data) *(.data.*) *(.gnu.linkonce.d.*) __data_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .got : { *(.got) } > mcb_ddr2_S0_AXI_BASEADDR .got1 : { *(.got1) } > mcb_ddr2_S0_AXI_BASEADDR .got2 : { *(.got2) } > mcb_ddr2_S0_AXI_BASEADDR .eh_frame : { *(.eh_frame) } > mcb_ddr2_S0_AXI_BASEADDR .jcr : { *(.jcr) } > mcb_ddr2_S0_AXI_BASEADDR .gcc_except_table : { *(.gcc_except_table) } > mcb_ddr2_S0_AXI_BASEADDR .sdata : { . = ALIGN(8); __sdata_start = .; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) __sdata_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .sbss (NOLOAD) : { . = ALIGN(4); __sbss_start = .; *(.sbss) *(.sbss.*) *(.gnu.linkonce.sb.*) . = ALIGN(8); __sbss_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .tdata : { __tdata_start = .; *(.tdata) *(.tdata.*) *(.gnu.linkonce.td.*) __tdata_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .tbss : { __tbss_start = .; *(.tbss) *(.tbss.*) *(.gnu.linkonce.tb.*) __tbss_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .bss (NOLOAD) : { . = ALIGN(4); __bss_start = .; *(.bss) *(.bss.*) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); __bss_end = .; } > mcb_ddr2_S0_AXI_BASEADDR _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); /* Generate Stack and Heap definitions */ .heap (NOLOAD) : { . = ALIGN(8); _heap = .; _heap_start = .; . += _HEAP_SIZE; _heap_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .stack (NOLOAD) : { _stack_end = .; . += _STACK_SIZE; . = ALIGN(8); _stack = .; __stack = _stack; } > mcb_ddr2_S0_AXI_BASEADDR _end = .; } I have not modified any files given in the demo. Can someone please help me figure out what to do so that the project compiles and can be programmed on my Atlys board? Thanks