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Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so. A single-ended clock interface in the board.xml file looks like this: <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description> <port_maps> <port_map logical_port="clk" physical_port="clk" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> Which allows one to click and drag "System Clock" from the board tab into the block design and gives you a clocking wizard with a single-ended clock. I want to be able to do the exact same thing, except instead of spawning a clocking wizard with a single-ended clock, it spawns a clocking wizard with a differential clock, like this: Here is my failed attempt at creating this interface: I used "xilinx.com:signal:diff_clock_rtl:1.0" instead of "xilinx.com:signal:clock_rtl:1.0" and added another port map for the p/n signals. <interface mode="slave" name="sys_clock" type="xilinx.com:signal:diff_clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Double-Ended 100MHz oscillator used as system clock on the board that don't work none good</description> <port_maps> <port_map logical_port="CLK_P" physical_port="clk_p" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_p"/> </pin_maps> </port_map> <port_map logical_port="CLK_N" physical_port="clk_n" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_n"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> and I added the following pins to my pin file: <?xml version="1.0" encoding="UTF-8" standalone="no"?> <part_info part_name="xc7a200tffg1156-2"> <pins> <pin index="00" name ="clk_p" iostandard="LVCMOS25" loc="AG29" /> <pin index="01" name ="clk_n" iostandard="LVCMOS25" loc="AG30" /> Which gives me this message: "'System Clock' board component cannot be connected because no possible options to connect." when I try to click and drag system clock into the design: Do I need to edit the preset file, or is the syntax for my interface definition incorrect, or am I missing something else entirely? Any help is greatly appreciated. Thanks in advance

Ubuntu 14.04 worked on ZYBO Z7-20, but at first Ethernet did not work. The cause was that MDIO of Ethrnet 0 of Peripheral I / O Pins of PS of ZYBO Z7 was connected to EMIO. In the circuit diagram of ZYBO Z7, MDIO is connected to MIO52, MIO53. In the board file, should I connect MDIO of Ethrnet 0 of PS Peripheral I / O Pins to MIO? https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf Currently, since we connected MDIO of Ethrnet 0 of Peripheral I / O Pins of PS of ZYBO Z7 to MIO, Ubuntu 14.04's Ethernet now works on ZYBO Z7-20. This situation was also the same for ZYBO. In previous ZYBO_zynq_def.xml, MIDO was connected to MIO.

I followed the directions on how to add the Diligent boards to Vivado for 2015 and later. I have 2016.4 and it did not work. You have to now go to board_parts and then Artix7 and then put the board files (that correspond to Artix) to make this work. It gives worthless errors if you do anything else.