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Found 5 results

  1. Hello Digilent Forum! I have been able to run the Cmod A7 Out of Box Demo and export it to an SDK/Vitis project, then modify memorytest.c to write and read new data to and from the SRAM. What a great demo for getting started with the Cmod A7! However, I would like to configure the external memory controller (AXI EMC) block to use its individual ports -- without using the Cmod A7 board file and the "cellular_ram" port from the EMC_INTF pin of the EMC block. I created a new project that uses the xc7a35tcpg236-1 FPGA (not the board file), edited the constraints XDC file, and pinn
  2. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about
  3. I am using zybo and block design flow to connect xadc ip to my system. But, the xadc is not giving out any info acquired from the outside. One forum mentioned that in case there is no instantiation xadc read internal voltage or temp. So I checked the wrapper and there is no instantiation of xadc. I am feeding the xadc with 100mhz clock. Should I change it? P. S; if I posted in the wrong forum please move my post. Thank you in advance for any help.
  4. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code...
  5. Hello, I have written many VHDL configurations, however, I am now working with block designs on VIVADO and am having trouble figuring out how to interconnect a binary counter with outputs Q[8:0] to inputs discrete logic ANDs ORs NOTs of various [?:?]. I need to do this so that I can determine multiple output values of the 9bit count. I would also need to know how to do this for other discrete logic circuits. Also any information about using wrappers to import the design into a VHDL usage would be helpful as that would be the next step. The specific trouble seems to be that whe