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Showing results for tags 'block design'.
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Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
I am using zybo and block design flow to connect xadc ip to my system. But, the xadc is not giving out any info acquired from the outside. One forum mentioned that in case there is no instantiation xadc read internal voltage or temp. So I checked the wrapper and there is no instantiation of xadc. I am feeding the xadc with 100mhz clock. Should I change it? P. S; if I posted in the wrong forum please move my post. Thank you in advance for any help.
I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
Hello, I have written many VHDL configurations, however, I am now working with block designs on VIVADO and am having trouble figuring out how to interconnect a binary counter with outputs Q[8:0] to inputs discrete logic ANDs ORs NOTs of various [?:?]. I need to do this so that I can determine multiple output values of the 9bit count. I would also need to know how to do this for other discrete logic circuits. Also any information about using wrappers to import the design into a VHDL usage would be helpful as that would be the next step. The specific trouble seems to be that when I connect Q[8:0] to OP[3:0] it just draws a bus and doesn't specify which actual pin configuration is present nor how to select which it should be. I have also gone thru several Xilinx reference materials on VIVADO and none of the techniques I have found demonstrate nor explain how to do this specific task. Thank you in advance Sincerely DC PS. 2 more considerations after I created this post 1) placing this circuit into a stand alone block IP circuit 2) Interconnecting directly TO FPGA IOs