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Found 11 results

  1. Is it possible to write a VERILOG / VHDL code to download the programming file (fpga bitstream) to the hardware device (for example an SPI flash memory)? I'm asking this, because I would like to transfer a bit stream into a spi flash memory, which will then be mounted on an fpga card for boot and configuration. I have already written a few lines of code to write, read, and erase the contents of the 32 MB NOR flash memory (PMODSF3). I tested my code and it works without problems! However, how to read the bitstream, before writing it to the flash memory? Do I only need to transfer the bitstream into flash memory or do I have to add a header and a footer in the memory before and after the transfer of the bitstream file? Have you ever worked on a similar project? N.B: I am using a Xilinx FPGA (Artix-7) on a customized board. I would like to find an alternative solution to the Xilinx hardware manager to program the SPI flash. Any ideas, feedbacks and suggestions are welcomed! Thank you Hervé
  2. this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  3. Trillian

    Bistream Size Quad SPI

    Hi there, I'm trying to program the arty using quad spi and I get the following error: [Writecfgmem 68-4] Bitstream at address 0x00000000 has size 2192012 bytes which cannot fit in memory of size 2097152 bytes. So I'm ~95kb short. Now I wonder what I can try to make my Bitstream smaller. Would I just try to shrink my cpp application?
  4. Hai ., i had bought DIGILENT Zybo Kit 7000 series Family. i had flashed the Zynq boot image with the following offset values successfully on Zynq Board via Xilinx SDK (ver: 2016.4) fsbl.elf system_wrapper.bit U-boot.elf U-image 0x600000 dtb file 0xA00000 ramdisk 0xA20000 But the FPGA done_led is not working automatically after a power cycle. on the other hand, if i program the FPGA MANUALLY via Xilinx SDK , it works and kernel image loads successfully from QSPI Flash. How to Make FPGA done_LED works automatically? Thanks in Advance..
  5. For bitstream encryption using battery-backed RAM, you are suppose to supply the Vccaux pin with voltage to keep the encryption key alive in memory. 1. Where is the Vccaux pin on the Cmod A7? (Hopefully it is not the VU pin because it would be really wasteful to power the whole FPGA just to keep the encryption key alive!) 2. What voltage is supposed to be supplied? Thanks, David
  6. Hi, I recently acquired a Basys 3 board and am currently trying to run the abacus demo on the board with a .bin file. I have been able to synthesize and implement all of the verilog files and followed all of the steps given in the demonstration video to run the project on the board , but I have not been able to generate the bitstream file. I attached a report file just in case someone wants to take a look at it. EDIT: I have found three errors but do not know what they mean. [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. bitstream_report.txt
  7. Hello, I am trying to program my Basys3 with a simple counter, that will count a sequence, per the push of one of the push buttons on the board. I cannot get the implementation to run, correctly, and i have attached my port assignments, as well as the error message. The whole project is attached as well, and my code is below. Thanks, Mike Code: library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity maina is port ( --Btnc : in std_logic; Clk : in std_logic; ClrN : in std_logic; Q : out std_logic_vector (2 downto 0)); end maina; architecture BEHAVIORAL of maina is signal Qint: std_logic_vector (2 downto 0); begin process(Clk) begin if Clk' event and Clk = '1' then if ClrN = '1' then Qint <= "000"; elsif ClrN = '0' then case Qint is when "000" => Qint <= "110"; when "110" => Qint <= "111"; when "111" => Qint <= "100"; when "100" => Qint <= "101"; when "101" => Qint <= "001"; when "001" => Qint <= "000"; when others => Qint <= "000"; end case; end if; end if; end process; Q <= Qint; end behavioral; Lab5_LUT_mod4.xpr
  8. Hi! I own Nexys4DDR approx 1 year. I'm using it only for finished cores, so I'm in VHDL even not yet beginner, sadly for lack of time I began not to learn. Can anybody help me to create bitstream selector for choose which bitstream will be loaded and used? Why this Q and what I mean under help: I'm using mostly few cores, but it's for me hard to accessible Nexys4DDR board to exchange microSD card, so I want to place them into one and onlly if I find new then change/add. Help: I'm not able to create own project in VHDL, I can only follow instructions with help of possible mismatch or error. If is any public core available for this purpose can anybody recommend me one? Really it looks: do it for me and I use it. Sadly it's similar, but not for my lazy mind and hands - I have no knowledge and when I go to compile any core I always learn anything about Vivado. I'm programmer in assembler of 8-bit computers and Visual Basic with beginning C++ and also website creating, so understand HTML and others. So VHDL is not hard to recognize any action in code, but it's different to watching work of any other like to create own. Thank you for understanding and help. Miro
  9. Hi! I'm here really new and I'm only beginning learn VHDL. I'm owner of Nexys4DDR and using it for first for Mega 65 and Apple II computer cores, now I want to use for own programming. First Q is maybe stupid, but very useful. I'm loading cores from microSD card and if I want to use one I must to select first card, when second, select second card... always push and pull any. I want to have all on one microSD card. How to create any core bitstream selector? If any, which programming language to use? Thank you for at least reading this. Miro
  10. Hello All, Just joined the forum, I just received my Arty board, and ported a very simple 32 bit counter design that drives LEDs (slower bits). I can synthesize and implement the design (no warnings), I can view the schematic and it looks exactly like the RTL, however, when I try to load it onto the target I get the following warning: WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. The board does nothing! I use this exact same code on another FPGA board (Altera Cyclone-5) and it works fine... I'm assuming that the above warning is critical because after the download the boards doesn't do anything Thanks for any help! -Paul
  11. I am using Nexys4DDR board, xc7a100t-1csg324. While using ISE 14.5 or ISE 14.7, synthesize and implementation are done without errors. But, while generating the bitstream to configure the FPGA chip, this step is stucked (i.e., Generating bitstream is running and never stop) without any error. Maybe with the same design without any modification, this step is completed normally but the many times it is not. please someone help me with this point.