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Found 15 results

  1. Hi, I'm looking to test out if I can send a bitstream to the artix7 Fpga from a Linux processor. To do so, I need to set all the mode pins to 3v3. In the schematic sheet for arty, I cant see from where the mode pins get connected to the fpga. My plan is to do a little circuit surgery to remove the spi flash. Would anyone be able to tell me how the mode pins hookup? Best, Konstantin
  2. this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  3. Hello everyone! I got my hands on a Diligent Nexys 2 Spartan 3E Board in this pandemic from a prof next doors. I am proficient in Verilog HDL and VHDL. I want to test my codes on this board, but in the board select menu, there is no option to select for this board. After Googling this stuff, I found that the production of this board has stopped. Is there any way in which I can program this board using Xilinx Vivado ISE / (or any other software)?
  4. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here
  5. Hello, I am a fairly new to using the Basys 3 and a student using it for a project. I am attempting to output 4 separate variables from the Pmod ports on the board using the JA Pmod part. When I run synthesis, implementation, and then bitstream, I get the same error for all but one of my outputs. My error message: [Common 17-69] Command failed: Site cannot be assigned to more than one port ["D:/LogicLab/SignalsProjectMK1/SignalsProjectMK1.srcs/constrs_1/new/BasysOut.xdc":16] Constraint: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk]
  6. Is it possible to write a VERILOG / VHDL code to download the programming file (fpga bitstream) to the hardware device (for example an SPI flash memory)? I'm asking this, because I would like to transfer a bit stream into a spi flash memory, which will then be mounted on an fpga card for boot and configuration. I have already written a few lines of code to write, read, and erase the contents of the 32 MB NOR flash memory (PMODSF3). I tested my code and it works without problems! However, how to read the bitstream, before writing it to the flash memory? Do I only need to transfer the
  7. Hi there, I'm trying to program the arty using quad spi and I get the following error: [Writecfgmem 68-4] Bitstream at address 0x00000000 has size 2192012 bytes which cannot fit in memory of size 2097152 bytes. So I'm ~95kb short. Now I wonder what I can try to make my Bitstream smaller. Would I just try to shrink my cpp application?
  8. Hai ., i had bought DIGILENT Zybo Kit 7000 series Family. i had flashed the Zynq boot image with the following offset values successfully on Zynq Board via Xilinx SDK (ver: 2016.4) fsbl.elf system_wrapper.bit U-boot.elf U-image 0x600000 dtb file 0xA00000 ramdisk 0xA20000 But the FPGA done_led is not working automatically after a power cycle. on the other hand, if i program the FPGA MANUALLY via Xilinx SDK , it works and kernel image loads suc
  9. For bitstream encryption using battery-backed RAM, you are suppose to supply the Vccaux pin with voltage to keep the encryption key alive in memory. 1. Where is the Vccaux pin on the Cmod A7? (Hopefully it is not the VU pin because it would be really wasteful to power the whole FPGA just to keep the encryption key alive!) 2. What voltage is supposed to be supplied? Thanks, David
  10. Hi, I recently acquired a Basys 3 board and am currently trying to run the abacus demo on the board with a .bin file. I have been able to synthesize and implement all of the verilog files and followed all of the steps given in the demonstration video to run the project on the board , but I have not been able to generate the bitstream file. I attached a report file just in case someone wants to take a look at it. EDIT: I have found three errors but do not know what they mean. [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IO
  11. Hello, I am trying to program my Basys3 with a simple counter, that will count a sequence, per the push of one of the push buttons on the board. I cannot get the implementation to run, correctly, and i have attached my port assignments, as well as the error message. The whole project is attached as well, and my code is below. Thanks, Mike Code: library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity maina is port ( --Btnc : in std_logic; Clk : in std_logic; ClrN : in std_logic;
  12. Hi! I own Nexys4DDR approx 1 year. I'm using it only for finished cores, so I'm in VHDL even not yet beginner, sadly for lack of time I began not to learn. Can anybody help me to create bitstream selector for choose which bitstream will be loaded and used? Why this Q and what I mean under help: I'm using mostly few cores, but it's for me hard to accessible Nexys4DDR board to exchange microSD card, so I want to place them into one and onlly if I find new then change/add. Help: I'm not able to create own project in VHDL, I can only follow instructions with help of possib
  13. Hi! I'm here really new and I'm only beginning learn VHDL. I'm owner of Nexys4DDR and using it for first for Mega 65 and Apple II computer cores, now I want to use for own programming. First Q is maybe stupid, but very useful. I'm loading cores from microSD card and if I want to use one I must to select first card, when second, select second card... always push and pull any. I want to have all on one microSD card. How to create any core bitstream selector? If any, which programming language to use? Thank you for at least reading this. Miro
  14. Hello All, Just joined the forum, I just received my Arty board, and ported a very simple 32 bit counter design that drives LEDs (slower bits). I can synthesize and implement the design (no warnings), I can view the schematic and it looks exactly like the RTL, however, when I try to load it onto the target I get the following warning: WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-
  15. I am using Nexys4DDR board, xc7a100t-1csg324. While using ISE 14.5 or ISE 14.7, synthesize and implementation are done without errors. But, while generating the bitstream to configure the FPGA chip, this step is stucked (i.e., Generating bitstream is running and never stop) without any error. Maybe with the same design without any modification, this step is completed normally but the many times it is not. please someone help me with this point.