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Found 3 results

  1. Hi everyone ! I have little project to do :displaying an image on PMOD Oled in VHDL Language. I took the Nexys4 vhdl project and tried to make it run, i have an Basys 3 Board,so i've just replaced some constraints with mine on the Board,and it gives me Failed Bitream Write:W5,J1,L1 are not valid site or package pin .Why are they not valid pins,Do I need to make extra stuff to make it work on this Different Board ? I'll attach the constraint file below.Thank you in Advance. Nexys4_Master.xdc
  2. Hello, i am trying to make a 4 bit counter that works with flipflops in VHDL. Now i have an issue related to how to make the code for the clock. I know It has to do with the oscillator in the basys and a frequency divider but i don't know how to unite thé code with the board. So, I really need help.
  3. Hi, Can anyone please help me with this code or any new code if you know. I am trying to interface servo motor with basys3. Please help me. In the code, I used in-built 'led' to verify the code first rather than trying on servo motor control pin. TOP MODULE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ServoUpDown is Port ( Clk : in STD_LOGIC; btnU : in STD_LOGIC; btnD : in STD_LOGIC; led : out STD_LOGIC); end ServoUpDown; architecture Behavioral of ServoUpDown is component Controller is Port ( btnD : in STD_LOGIC; btnU : in STD_LOGIC; Position : out STD_LOGIC_VECTOR (7 downto 0)); end component; component ServoD is Port ( Clk : in STD_LOGIC; Position : in STD_LOGIC_VECTOR (7 downto 0); led : out STD_LOGIC); end component; signal Position : std_logic_vector (7 downto 0); begin Servo1: ServoD port map (Clk, Position, led); Controller1: Controller port map (btnD, btnU, Position); end Behavioral; SERVO DIRECTION: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ServoD is Port ( Clk : in STD_LOGIC; Position : in STD_LOGIC_VECTOR (7 downto 0); led : out STD_LOGIC); end ServoD; architecture Behavioral of ServoD is constant ClockDiv: integer := 63; signal ClockTick: std_logic := '0'; signal ClockCount: std_logic_vector (6 downto 0) := "0000000"; signal PulseCount: std_logic_vector (11 downto 0) := "000000000000"; begin process (Clk) begin if Clk='1' and Clk'event then if ClockCount = ClockDiv-2 then ClockTick <= '1'; else ClockTick <= '0'; end if; if ClockTick='1' then ClockCount <= "0000000"; else ClockCount <= ClockCount + 1; end if; end if; end process; process (Clk) begin if Clk='1' and Clk'event then if ClockTick='1' then PulseCount <= PulseCount + 1; end if; if PulseCount < ("0001" & Position) then led <= '1'; else led <= '0'; end if; end if; end process; end Behavioral; SERVO CONTROLLER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Controller is Port ( btnD : in STD_LOGIC; btnU : in STD_LOGIC; Position : out STD_LOGIC_VECTOR (7 downto 0)); end Controller; architecture Behavioral of Controller is signal ServoPos: unsigned(7 downto 0):= "00000000" ; signal Button: std_logic; signal Direction: std_logic; begin process (Button) begin if Button='1' and Button'event then if Direction='1' then ServoPos <= ServoPos + 4; Position <= conv_std_logic_vector(ServoPos, 8); else ServoPos <= ServoPos - 4; Position <= conv_std_logic_vector(ServoPos, 8); end if; end if; end process; Button <= btnD xor btnU; Direction <= btnU and not btnD; end Behavioral; I tried but it does not work. Can any one help me how to write vhdl code to interface servo motor to Basys3?