Search the Community

Showing results for tags 'basys3'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions


  • Community Calendar

Found 97 results

  1. Basys 3 D1-8 components

    Hello, I am trying to understand the protection mechanism of the I/O pins on the Basys 3, and would like more information about components D1-8 on the first page of the schematic. Could someone please tell me the part number? Best, Zen
  2. Hello I want to send an image from nexys4 DDR to basys3 through pmod. Is it possible? If yes then how to connect them. Nexys4 DDR will be master device.
  3. I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider code for the 7 seven of the basys3 by my instructor and I managed to do the stopwatch. When I changed all my constraints to the PMOD pins and connect to the external 7 segment I can see that it works because it stops and resets but it does the counting so quickly that I can't read at all. I am thinking that the problem may be because of the clock divider and the frequency of the clocks. The given code states that since the original clock of the basys3 is 100 MHz a counter will count up to 500000 to obtain a 100 hz and another counter will count up to 208334 that is 240 Hz. First of all I didn't understand why the second clock is 240 Hz and why do the counters count up to these irrelivant numbers. Secondly what can I do for the external 4 bit 7 segment to slow it down?
  4. Hello, I am attempting to communicate to a Pmod RF2: IEEE 802.15 RF Transceiver with a Basys3 board using the SPI protocol in VHDL. The microchip on the pmod is the MRF24J40. How do I identify the address of the MRF24J40? To my understanding, if I want to write/read a memory location on the MRF24J40, I need to send the address followed by the address of the specific memory location on the MRF24J40. Is it written on the microchip itself? The master and slave SPI modules that I am attempting to use are linked to this post. The documentation for the master and slave links are below. The specification sheets for the pmod and MRF24J40 are included as well. Master: Slave: Pmod: Interface_Specification.pdf MRF24J40: Thank you. spi_slave.vhd spi_master.vhd
  5. Basys3 Multiplier Question

    Hello, I am making a project to make the XADC read voltages, and I want to multiply the voltages from channel 1 and channel 2, do I need to send the two voltages to the multiplier at the same time? And if there is a delay when I get those two voltages, how can I send them at the same time. New to the FPGA, please help me. Thanks in advance.
  6. Is there no other way?

    Greetings, I am trying to build a very simple digital signal processing circuit into my FPGA, Basys 3 board. Below you can find a simple block diagram. As you can see the components are, - A clock converter - An ADC ( embedded xadc) - A digital filtering operation H(e^jw) ( simple addition, multiplication circuit) - An SPI bus for communicating with an external DAC I have managed to build the clock converter, and the filtering operation. However, I have failed over and over again at building SPI and ADC blocks. Especially the XADC block gave me ( and still giving ) a hard time. I am aware that programming FPGAs can be very challenging. However, my question is... Is there no other way to do it? No simpler way to program my Basys 3 ? I have spent a good amount of time studying how to work with IP blocks, and the block diagram feature of Vivado. However, it does not work. Or I should at least say, it is not straight forward in any sense. It is not user friendly. My block diagram is really really simple. I connect all the necessary connections. Clock to clock, data out to.. etc. But I can't even get an analog reading on my Basys 3. Last but not least, there aren't any tutorials on working with XADC. The video about Basys 3 XADC, made by Xilinx, is a total joke. The other video, "teaching" how to use the IP generator for XADC is also another joke. These are 2-3 min videos, just showing you that IP generation feature does exist. They do not show how to use it in any way. This whole text is not a proper question, I am aware of that. Yet I am open to anything. Suggest me another, simpler way to code FPGAs. Suggest me another, more user friendly device. Suggest me an alternative platform to develop digital signal processing algorithms. Please. Sincerely, Berk
  7. Dear Digilent, I have a simple design on a BASYS3, which contains a MICROBLAZE, a LED and two PUSH BUTTONS. I can control how fast the LED is blinking by pressing the PUSH BUTTONS. The BITSTREAM of that design is stored in a non-volatile serial Flash device, which is attached to the ARTIX-7 FPGA using a dedicated quad-mode (x4) SPI bus. When the system starts, the contents of the flash memory are read and the FPGA is configured normally. I would like to be able to memorize the latest configuration of the PUSH BUTTONS in a non-volatile memory, so that the system at startup can use that configuration. In other words, I would like to allow the user, the option to write in a non-volatile memory, the latest configuration of the push buttons, without having to change the BITSTREAM all the time. Something likes partitioning non-volatile memory into two sections: 1- One section will be to store the BITSTREAM for configuration during system startup. 2- The other section will be to allow the user to read, modify (write) and save parameters for the next startup. Is it possible to do this with the BASYS3? If so, could you please advise me how to do it? If not, what kind of system would be needed to achieve this? Thank you in advance for any suggestions and advices. Regards, H
  8. This little module might be of use to somebody - it sends 16-bit values to an external serial device, as four ascii hexidecimal digits (eg "12AB"), with new lines and carriage returns. The sample design send the settings of the 16 slide switches every time the center button is pressed.
  9. Implementation SPI basys3

    Hi, I need your help please, actually I am work in an arduino communication with FPGA (Basys3), but i have a problem with the implementation, can you help me? VHDL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SPI_rx3_top is Port ( SCK : in STD_LOGIC; -- SPI input clock DATA : in STD_LOGIC; -- SPI serial data input CS : in STD_LOGIC; -- chip select input (active low) led : out STD_LOGIC_VECTOR (7 downto 0) := X"FF"); end SPI_rx3_top; architecture Behavioral of SPI_rx3_top is signal dat_reg : STD_LOGIC_VECTOR (7 downto 0); begin process (SCK) begin if (SCK'event and SCK = '1') then -- rising edge of SCK if (CS = '0') then -- SPI CS must be selected -- shift serial data into dat_reg on each rising edge -- of SCK, MSB first dat_reg <= dat_reg(6 downto 0) & DATA; end if; end if; end process; process (CS) begin if (CS'event and CS = '1') then -- update LEDs with new data on rising edge of CS led <= not dat_reg; end if; end process; end Behavioral; XDC: ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {CS}] set_property IOSTANDARD LVCMOS33 [get_ports {CS}] ##Sch name = JB2 set_property PACKAGE_PIN A16 [get_ports {DATA}] set_property IOSTANDARD LVCMOS33 [get_ports {DATA}] ##Sch name = JB3 set_property PACKAGE_PIN B15 [get_ports {SCK}] set_property IOSTANDARD LVCMOS33 [get_ports {SCK}] Warnings: [Place 30-876] Port 'SCK' is assigned to PACKAGE_PIN 'B15' which can only be used as the N side of a differential clock input. Please use the following constraint(s) to pass this DRC check: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SCK_IBUF}] [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances
  10. Prompted by another thread here ( ), I've been experimenting the the Dynamic Reconfiguration Port on the Artix-7 MMCM You can find the code and constraints for the Basys3 here: It might be of interest to somebody (e.g. to change a VGA clock frequency dynamically).
  11. basys 3

    how to implement 32 bit fma logic can be implemented on basys 3 kit.
  12. BASYS3 VGA Output Out of Range problem

    Hello everyone, I just started learning VHDL and digital design on my college and as a term project I am to design a digital circuit which will output a game through VGA pins. I first started examining examples on the internet and tried to synthetise myself on Vivado Design Suite. However, I encountered problems. The following is the code which I use to synchronize image. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sync_module is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; start : in STD_LOGIC; y_control : out STD_LOGIC_VECTOR (9 downto 0); x_control : out STD_LOGIC_VECTOR (9 downto 0); h_s : out STD_LOGIC; v_s : out STD_LOGIC; video_on : out STD_LOGIC); end sync_module; architecture Behavioral of sync_module is -- Video Parameters constant HR:integer:=1280;--Horizontal Resolution constant HFP:integer:=48;--Horizontal Front Porch constant HBP:integer:=248;--Horizontal Back Porch constant HRet:integer:=112;--Horizontal retrace constant VR:integer:=1024;--Vertical Resolution constant VFP:integer:=1;--Vertical Front Porch constant VBP:integer:=38;--Vertical Back Porch constant VRet:integer:=3;--Vertical Retrace --sync counter signal counter_h,counter_h_next: integer range 0 to 799; signal counter_v,counter_v_next: integer range 0 to 524; --mod 2 counter signal counter_mod2,counter_mod2_next: std_logic:='0'; --State signals signal h_end, v_end:std_logic:='0'; --Output Signals(buffer) signal hs_buffer,hs_buffer_next:std_logic:='0'; signal vs_buffer,vs_buffer_next:std_logic:='0'; --pixel counter signal x_counter, x_counter_next:integer range 0 to 900; signal y_counter, y_counter_next:integer range 0 to 900; --video_on_off signal video:std_logic; begin --clk register process(clk,reset,start) begin if reset ='1' then counter_h<=0; counter_v<=0; hs_buffer<='0'; hs_buffer<='0'; counter_mod2<='0'; elsif clk'event and clk='1' then if start='1' then counter_h<=counter_h_next; counter_v<=counter_v_next; x_counter<=x_counter_next; y_counter<=y_counter_next; hs_buffer<=hs_buffer_next; vs_buffer<=vs_buffer_next; counter_mod2<=counter_mod2_next; end if; end if; end process; --video on/off video <= '1' when (counter_v >= VBP) and (counter_v < VBP + VR) and (counter_h >=HBP) and (counter_h < HBP + HR) else '0'; --mod 2 counter counter_mod2_next<=not counter_mod2; --end of Horizontal scanning h_end<= '1' when counter_h=799 else '0'; -- end of Vertical scanning v_end<= '1' when counter_v=524 else '0'; -- Horizontal Counter process(counter_h,counter_mod2,h_end) begin counter_h_next<=counter_h; if counter_mod2= '1' then if h_end='1' then counter_h_next<=0; else counter_h_next<=counter_h+1; end if; end if; end process; -- Vertical Counter process(counter_v,counter_mod2,h_end,v_end) begin counter_v_next <= counter_v; if counter_mod2= '1' and h_end='1' then if v_end='1' then counter_v_next<=0; else counter_v_next<=counter_v+1; end if; end if; end process; --pixel x counter process(x_counter,counter_mod2,h_end,video) begin x_counter_next<=x_counter; if video = '1' then if counter_mod2= '1' then if x_counter= 639 then x_counter_next<=0; else x_counter_next<=x_counter + 1; end if; end if; else x_counter_next<=0; end if; end process; --pixel y counter process(y_counter,counter_mod2,h_end,counter_v) begin y_counter_next<=y_counter; if counter_mod2= '1' and h_end='1' then if counter_v >32 and counter_v <512 then y_counter_next<=y_counter + 1; else y_counter_next<=0; end if; end if; end process; --buffer hs_buffer_next<= '1' when counter_h < 704 else--(HBP+HGO+HFP) '0'; vs_buffer_next<='1' when counter_v < 523 else--(VBP+VGO+VFP) '0'; --outputs y_control <= conv_std_logic_vector(y_counter,10); x_control <= conv_std_logic_vector(x_counter,10); h_s<= hs_buffer; v_s<= vs_buffer; video_on<=video; end Behavioral; ...and the following is a snippet from my constraints file : set_property PACKAGE_PIN N19 [get_ports {rgb[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] set_property PACKAGE_PIN J18 [get_ports {rgb[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] set_property PACKAGE_PIN D17 [get_ports {rgb[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] set_property PACKAGE_PIN P19 [get_ports h_s] set_property IOSTANDARD LVCMOS33 [get_ports h_s] set_property PACKAGE_PIN R19 [get_ports v_s] set_property IOSTANDARD LVCMOS33 [get_ports v_s] ## END VGA CONNECTOR I went through google results for this "out of range" problem and none of them solved my problem. Then I connected my oscilloscope to the output of the horizontal sync and vertical sync. This is from the 13 pin of the VGA output : And this is the output of the 14. pin: So what do you think my problem is? The default demo on BASYS3 runs flawlessly.
  13. This is a response question to an earlier thread that I was not able to continue. I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. "ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8" I've tried it with 6, 8 and even all 32-bits and I get the same failure. Code: inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => '1', s_axis_phase_tdata => cntr(31 downto 24), -- this is line 82 of Wave_top.vhd m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); LOG DATA: Vivado Simulator 2016.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 0fc31941c582466d8f4474edc8fb8bef --debug typical --relax --mt 2 -L xbip_utils_v3_0_7 -L axi_utils_v2_0_3 -L xbip_pipe_v3_0_3 -L xbip_bram18k_v3_0_3 -L mult_gen_v12_0_12 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_3 -L xbip_dsp48_multadd_v3_0_3 -L dds_compiler_v6_0_13 -L xil_defaultlib -L secureip -L xpm --snapshot Wave_top_behav xil_defaultlib.Wave_top -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8 [C:/Users/Toshiba-/coregen_sinewave/coregen_sinewave.srcs/sources_1/new/Wave_top.vhd:82] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit wave_top in library work failed.
  14. I am trying to determine if and how a Vivado IP Core can be used to create and audible tone. I have been reviewing the DSS Compiler 6.0 product guide and simulation tutorial ug937. I have configured it as shown in the attached image. I understand the sine wave output should be bits (10 downto 0) of "m_axis_data_tdata". It is asking for s_axis_phase_tvalid, s_axis_phase_tdata for input. I cannot seem to get a clear understanding of what these are. Can someone explain in layman's terms? I also created a clock divider to drop aclk down to 12kHz as an attempt the get my sine wave into the audible range. I get no output on the board or in the simulator. Ideas???
  15. Built in Self Test - Basys3 Board

    Hi all, I am a new user of basys3 board and I need your help about the "Built in Self Test " of this link Can you share me the source code of this self test and the IP cores used to this self test. Regards,
  16. Audio Output from BASYS3

    I am working on a school project making a sound (tone/ multi-tone) generator using a BASYS3 and Vivado. I am having trouble getting the sound part out. As a test I wrote a simple VHDL program to create a 357Hz square wave. I declared an output bit 'dataout'. I ran a simulation using Aldec-HDL Student Edition and I am getting the output squareware. I am using the PmodAMP2 connected to JB1 top row. In my xdc file I have dataout assigned to A14 ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {dataout}] set_property IOSTANDARD LVCMOS33 [get_ports {dataout}] I have connected stereo headphones to the PmodAMP2 jack. I get NO sound output. To test my board and program I set all the leds to light thru the counter. They work and flicker at different rates relative to where they are in the counter. But still no sound. What I am doing wrong? Is PmodAMP2 the right add-on to use or should I try PmodR2R? It shouldn't matter, but are the headphones causing the issue? The ref. sheet says 2.5 watt output. I also have questions about outputting integer values to the PmodAMP2 or PmodR2R. The BASYS3 and Pmod Reference manuals are not helping. One of my planned files has an integer range -92000 to 92000 (roughly). Please help!
  17. Pmod Wifi board with Basys3

    Hello, I am very new to FPGA so please bare with me. I am having a Pmod Wifi board and a Basys3 FPGA board and a Nexus4 Board. I need guidance for simple running tutorial of the Wifi with FPGA. A VHDL/Verilog based code sample will help a lot. I have tried to implement a microblaze based design in Vivado but i m very bad at it and could get success. Can any one help?? Thank you in advance.
  18. BASYS 3 Mouse QSPI

    Why BASYS 3 USB mouse unrecognized when using QSPI? Basys 3 can be programmed to use mouse. Mouse is recognized and usable using a bit file. But when a bin file is used, the JP1 jumper needs to be moved to QSPI and the mouse movement and buttons do nothing. How can the USB Mouse be made functional after booting with jumper in the QSPI position?
  19. Problems downloading to flash

    Hi, I'm new to FPGAs, so I purchased a BASYS3 to play around with. In following the "Getting Started with BASYS 3" video (youtube), I cannot save e a configuration to a memory device as that option is grayed out in my case (see attached screen capture). Does anyone have any ideas what's causing this and how to overcome it? Thanks in advance
  20. PmodMIC with BASYS 3

    Hello everyone, I'm doing a little project where I use a PmodMIC and a Digilent BASYS 3 board. I understand all the code that is been given (, but I want to get the data to the leds on my board. My goal is to show how loud it is in a room on the leds. So for example if it's very loud all the leds shine, if it's not so loud only a few leds brighten up. But I don't know how I get the DATA on my leds, en how to see what loud or soft is, can someone help me with that? Also, if I put my PmodMIC on connector JA , what do I have to change in my entity/.XDC file? Thanks for reading and answering! Small_vhdl_projects guy
  21. High speed pmod connectors maximum speed

    Hii All, Can I use AD-9266-80ebz evaluation board standalone with the basys-3 or zybo board. If yes, than what connectors I need to interface these boards. What is the maximum data rate that high speed Pmod connectors can support in zybo or basys-3. thank you for your help. Abhijeet
  22. Real Time Simulation basys3

    Hi! I'm currently implementing a game with led matrix using basys3. But sometimes it become hard to understand the mistake in the code if there is a problem with the code. I know how to use testbenches but in my case it's not really helpful. So I want to make a simulation with real time physical inputs. I mean the simulation show the results when I press a push button. Is it possible?
  23. I want to use the flash memory of 32Mbits of the basys 3, to write data in hexadecimal, I am using microblaze and the IP block axi quad spi, I have configured the hardware in vivado, i have included the soft-core microblaze and I have added the IP block Axi_quad_spi and I have connected the ext_spi_clk, s_axi_aclk (synchronously), with the 100 MHz clock, automatically vivado connected the outputs to the pins of the flash memory of the basys 3 card, so my question is: to program the memory in the SDK of xilinx, is there an example already done with this memory ?, or how can i program it?
  24. Hello, I am trying to program my Basys3 with a simple counter, that will count a sequence, per the push of one of the push buttons on the board. I cannot get the implementation to run, correctly, and i have attached my port assignments, as well as the error message. The whole project is attached as well, and my code is below. Thanks, Mike Code: library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity maina is port ( --Btnc : in std_logic; Clk : in std_logic; ClrN : in std_logic; Q : out std_logic_vector (2 downto 0)); end maina; architecture BEHAVIORAL of maina is signal Qint: std_logic_vector (2 downto 0); begin process(Clk) begin if Clk' event and Clk = '1' then if ClrN = '1' then Qint <= "000"; elsif ClrN = '0' then case Qint is when "000" => Qint <= "110"; when "110" => Qint <= "111"; when "111" => Qint <= "100"; when "100" => Qint <= "101"; when "101" => Qint <= "001"; when "001" => Qint <= "000"; when others => Qint <= "000"; end case; end if; end if; end process; Q <= Qint; end behavioral; Lab5_LUT_mod4.xpr
  25. Hello, guys. I am working on a CORDIC project with Basys3 board now. I had an unusual issue: my simulation shows the correct functionality of the circuit. But when I generated bit stream file and program the board. The hardware behaved totally differently with the simulation. And there is no difference if I change the clock period of the FSM. So I am wondering if anyone encountered similar problem before and how you solved this problem. Thank you so much. readme.txt top_lab8.xdc tb_ctrlnew.v