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Found 114 results

  1. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  2. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. Is the connection is ok? What will be other connections needed?
  3. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port( clk : in std_logic; rst : in std_logic; start : in std_logic; input : in std_logic_vector(7 downto 0); done : out std_logic; output : out std_logic; showstates: out std_logic_vector(3 downto 0) ); end entity; architecture dataflow of rs232_omo is type states is (idle_state,start_state,send_state,stop_state); signal present_state,next_state : states; signal data,data_next : std_logic; begin process(clk,rst) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin if rst='1' then present_state<=idle_state; count:=0; data<='1'; elsif rising_edge(clk) then present_state<=next_state; count:=count+1; index:=index+1; data<=data_next; end if; end process; process(present_state,data,clk,rst,start) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin done<='0'; data_next<='1'; case present_state is when idle_state => showstates<="1000"; data_next<='1'; if start='1' and rst='0' then count:=count+1; if count=clk_max then next_state<=start_state; count:=0; end if; end if; when start_state => showstates<="0100"; data_next<='0'; count:=count+1; if count=clk_max then next_state<=send_state; count:=0; end if; when send_state => showstates<="0010"; count:=count+1; data_next<=input(index); if count=clk_max then if index=7 then index:=0; next_state<=stop_state; else index:=index+1; end if; count:=0; end if; when stop_state => showstates<="0001"; count:=count+1; if count=clk_max then next_state<=idle_state; done<='1'; count:=0; end if; end case; end process; output<=data; end architecture; Constraints: set_property PACKAGE_PIN V17 [get_ports {input[0]}] set_property PACKAGE_PIN V16 [get_ports {input[1]}] set_property PACKAGE_PIN W16 [get_ports {input[2]}] set_property PACKAGE_PIN W17 [get_ports {input[3]}] set_property PACKAGE_PIN W15 [get_ports {input[4]}] set_property PACKAGE_PIN V15 [get_ports {input[5]}] set_property PACKAGE_PIN V14 [get_ports {input[6]}] set_property PACKAGE_PIN W13 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[0]}] set_property PACKAGE_PIN L1 [get_ports {showstates[3]}] set_property PACKAGE_PIN P1 [get_ports {showstates[2]}] set_property PACKAGE_PIN N3 [get_ports {showstates[1]}] set_property PACKAGE_PIN P3 [get_ports {showstates[0]}] set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN R2 [get_ports rst] set_property PACKAGE_PIN T1 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports done] set_property IOSTANDARD LVCMOS33 [get_ports output] set_property PACKAGE_PIN V3 [get_ports done] set_property PACKAGE_PIN V13 [get_ports output] My testbench simulation got attached. And on-board, apparently I stuck with 'idle_state'. For any kind of help, I thank y'all in advance.
  4. Hi, I have been familiarizing myself with VHDL and FPGAs in general with the Digilent Basys3 board. Recently I have tried incorporating the Microblaze in to my design just to familiarize myself with it. I have created a simple block diagram where I connect a custom AXI-stream counter to an AXI-DMA block. The counter just streams incrementing numbers and adds the tlast signal to generate frames. My purpose is to develop a minimum working example on AXI-DMA transfer. I plan to transfer x-number of samples generated by the AXI-stream counter with the AXI-DMA to a BRAM memory. On programming the AXI-DMA core I have followed the Xilinx manual PG021 https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf section Direct Register Mode (Simple DMA) on page 71. Initializing the DMA works. However, after sending the transfer command to the DMA no transaction happens. I wonder whether the problem is in my C-code or the block diagram. I have verified with the vivado ILA that the counter is working and produces a stream of data. In addition I have tied tkeep port to logical high on the s2mm port on the DMA. Is it possible I have forgotten something else? Any suggestions will be warmly welcomed. top_module.pdfAXI_DMA_minimum_example.c
  5. fpga_babe

    HID protocol on Basys3

    Hi, I am using Basys3 board and I want to write a RTL module in FPGA to get the character from USB Keyboard. From the Digilent reference of basys3, if the FPGA side only receive the data from Keyboard, then the PS_CLK and PS_DAT ports can be as input direction. My question is that, to receive the keycode from a keyboard, do we need to send configuration to Keyboard before hand ?
  6. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am using the Vivado IP Catalog for generating the clock signal and the 4 binary counters(2) used on each 7-Segiment display digit. The Verilog code and constraint file are attached. The binary counter configuration: Implementing using: Fabric Output width: 4 [3:0] Increment Value (Hex): 1 Restrict Count (Hex): 4, 5, 9, 9 (7seg from left ro right) Count Mode: UP Clock Enable (CE): Checked Synchronous Clear(SCLR): Checked Init Value:(Hex): 0 Synchronous Controls and Clock Enable(CE) Priority: Sync Overrides CE Latency Configuration: Manual, 1 Feedback Latency Configuration: Manual, 0 I suspect I am overseeing/forgetting somewhere a simple detail. Any help/clarification is appreciated. Cheers, Rafael. (1) https://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Design/2015x/Verilog/docs-pdf/lab9.pdf (2) https://www.xilinx.com/support/documentation/ip_documentation/counter_binary/v12_0/pg121-c-counter-binary.pdf lab9_3_1.v Basys-3-Master.xdc
  7. Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-programming-guide/start). I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the sw_led.v file and a Basys3_sw_Demo.xdc constraint file. After downloading the files, building the project, then running the synthesis I get 26 critical warnings that cause the Implementation and Generate BitStream to fail. 22 of the critical warnings are "V17 is not a valid site or package pin name" (and each of the following 21 warnings change the "V17" to the next pin name in the constraint file. (I've checked the schematic and the Pin Names ARE VALID) The next critical warning is "Setting property "IOSTANDARD' is not allowed for GT Terminals and this error is flagging only a single line in the constraint file yet ALL of the switches in the constraint file all do a "set_property IOSTANDARD LVCM0S33......... The final 2 critical warnings are "Cannot set LOC property of ports. Site location is not valid. This error is flagging two of the LED settings in the contraint file yet, once again, all 16 of the LED's are using the same commands within the constraint file. I'm at a brick wall trying to figure out what the heck the problem is here. As I said...the 1st Tutorial went fine. This tutorial even included the constraint file needed for the project. I've attached a zip file containing the entire Vivado project. Any help/advice would be greatly appreciated. THANKS! project_2.zip
  8. Hello, I am designing a project in which I need to register the input from a 4x4 matrix KeyPad (this model) and to do so I have written the following VHDL test code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Display is Port ( selected : in std_logic; Row_Vector : in std_logic_vector(3 downto 0); Col_Vector : in std_logic_vector(3 downto 0); display_code : out std_logic_vector(6 downto 0); display_ctrl : out std_logic_vector(3 downto 0) ); end Display; architecture Behavioral of Display is signal Displayed : std_logic_vector(3 downto 0); begin process(Displayed) begin case Displayed is when "0000" => display_code <= "0000001"; -- "0" when "0001" => display_code <= "1001111"; -- "1" when "0010" => display_code <= "0010010"; -- "2" when "0011" => display_code <= "0000110"; -- "3" when "0100" => display_code <= "1001100"; -- "4" when "0101" => display_code <= "0100100"; -- "5" when "0110" => display_code <= "0100000"; -- "6" when "0111" => display_code <= "0001111"; -- "7" when "1000" => display_code <= "0000000"; -- "8" when "1001" => display_code <= "0000100"; -- "9" when "1010" => display_code <= "0000010"; -- a when "1011" => display_code <= "1100000"; -- b when "1100" => display_code <= "0110001"; -- C when "1101" => display_code <= "1000010"; -- d when "1110" => display_code <= "0110000"; -- E when "1111" => display_code <= "0111000"; -- F when others => display_code <= "1111111"; end case; end process; process(selected,Row_Vector,Col_Vector) begin if selected = '0' then Displayed <= Row_Vector; else Displayed <= Col_Vector; end if; end process; display_ctrl <= "1110"; end Behavioral; I have attached all the source code for my test, which includes a button debouncer (U18 button), which I push to show the value that I read from the A14,A16,B15 and B16 pins for the rows and A15,A17,C15 and C16 for the columns of the KeyPad. For example: when there are no cables connected to the row pins and I have not pushed the button, the value read from the row pins is shown in the 7-Segment display, which is "1111" (F). This means that when I connect a cable on any of the pins, a '0' is written at the input pin. If I connect a cable at the first row pin, the value read is "1110" and E is displayed. Following this logic, when I connect a cable to the second row pin and I leave the other ones disconnected, it should be displayed D ("1101") but instead 8 is displayed, which corresponds to "1000", which would mean that I have row 1, row 2 and row 3 cables connected, which is not the case. What could be the problem here? My main problem is to undestand how to communicate the keypad with the Basys3 FPGA Test_Code.zip
  9. When I try to program my board after I generated the .bit/.bin files, i get the following error [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121]Check to make sure the cable targets connected to this machine are properly connectedand powered up, then use the disconnect_hw_server and connect_hw_server commandsto re-register the hardware targets.it says no hardware exists on the server, even though my board is plugged in with the mode jumper in the JTAG position. I also tried reinstalling Vivado to make sure the cable drivers were installed.
  10. Hello everyone , I'm realtively new in programming FPGA's and needed some help . My micro-usb port got shorted so i had to resort to programming my basys-3 with a usb drive . I followed the reference file from digilent on that and everything was working fine . I used it the same way for the next few months . I stopped using the board for a months after and when i tried programming it today again , the bit file did got programmed . INstead the busy led next to the port forever keeps blinking . I tried formatting with FAT32 , resetting , testing the demo file on QSPI but nothing works even after all that . Like i said i'm very new to fpga's and mosty just implement basic codes to learn so i'm clueless when it comes to the next step . Any help would be apppreciated . Thank you . Regards, Supriya
  11. Hi! We are working with a Basys-3 FPGA and were wondering if it is possible to read large data files from a USB stick. We are trying to let the Basys 3 produce music through a module, but the internal ROM/Flash storage of the Basys is too small for, for instance, .Wav files or .Wav converted to .coe files. Is there a possibility to use the USB stick support for programming for this application or perhaps another method? Thanks! Kind regards, Jonathan
  12. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clock : in std_logic; -- 100MHz onboard oscillator trigger : in std_logic; -- assert to sample ADC diffn : in std_logic; -- single/differential inputs channel : in std_logic_vector(2 downto 0); -- channel to sample -- data output Dout : out std_logic_vector(14 downto 0); -- data from ADC OutVal : out std_logic; -- pulsed when data sampled -- ADC connection adc_miso : in std_logic; -- ADC SPI MISO adc_mosi : out std_logic; -- ADC SPI MOSI adc_cs : out std_logic; -- ADC SPI CHIP SELECT adc_clk : out std_logic -- ADC SPI CLOCK ); end ADC; architecture behavioural ofADC is -- clock signal adc_clock : std_logic := '0'; -- command signal trigger_flag : std_logic := '0'; signal sgl_diff_reg : std_logic; signal channel_reg : std_logic_vector(2 downto 0) := (others => '0'); signal done : std_logic := '0'; signal done_prev : std_logic := '0'; -- output registers signal val : std_logic := '0'; signal D : std_logic_vector(9 downto 0) := (others => '0'); -- state control signal state : std_logic := '0'; signal spi_count : unsigned(4 downto 0) := (others => '0'); signal Q : std_logic_vector(9 downto 0) := (others => '0'); begin -- clock divider -- input clock: 100Mhz --100MHz/1.3MHz = 74/2 -- adc clock: 1.3MHz clock_divider : process(clock) variable cnt : integer := 0; begin if rising_edge(clock) then cnt := cnt + 1; if cnt = 37 then cnt := 0; adc_clock <= not adc_clock; end if; end if; end process; -- produce trigger flag trigger_cdc : process(adc_clock) begin if rising_edge(adc_clock) then if trigger = '1' and state = '0' then sgl_diff_reg <= diffn; channel_reg <= channel; trigger_flag <= '1'; elsif state = '1' then trigger_flag <= '0'; end if; end if; end process; adc_clk <= adc_clock; adc_cs <= not state; -- SPI state machine (falling edge) adc_sm : process(adc_clock) begin if adc_clock'event and adc_clock = '0' then if state = '0' then done <= '0'; if trigger_flag = '1' then state <= '1'; else state <= '0'; end if; else if spi_count = "10000" then spi_count <= (others => '0'); state <= '0'; done <= '1'; else spi_count <= spi_count + 1; state <= '1'; end if; end if; end if; end process; -- Register sample outreg : process(adc_clock) begin if rising_edge(adc_clock) then done_prev <= done; if done_prev = '0' and done = '1' then D <= Q; Val <= '1'; else Val <= '0'; end if; end if; end process; -- LED outputs PROCESS (adc_clock) BEGIN IF (adc_clock'EVENT AND adc_clock = '1') THEN CASE D(9 DOWNTO 6) IS WHEN "0001" => Dout <= "000000000000011"; WHEN "0010" => Dout <= "000000000000111"; WHEN "0011" => Dout<= "000000000001111"; WHEN "0100" => Dout <= "000000000011111"; WHEN "0101" => Dout <= "000000000111111"; WHEN "0110" => Dout <= "000000001111111"; WHEN "0111" => Dout <= "000000011111111"; WHEN "1000" => Dout <= "000000111111111"; WHEN "1001" => Dout <= "000001111111111"; WHEN "1010" => Dout <= "000011111111111"; WHEN "1011" => Dout <= "000111111111111"; WHEN "1100" => Dout <= "001111111111111"; WHEN "1101" => Dout <= "011111111111111"; WHEN "1110" => Dout <= "111111111111111"; WHEN "1111" => Dout <= "111111111111111"; WHEN OTHERS => Dout <= "000000000000001"; END CASE; END IF; -- END IF; END PROCESS; OutVal <= Val; -- MISO shift register (rising edge) shift_in : process(adc_clock) begin if adc_clock'event and adc_clock = '1' then if state = '1' then Q(0) <= adc_miso; Q(9 downto 1) <= Q(8 downto 0); end if; end if; end process; -- Decode MOSI output shift_out : process(state, spi_count, sgl_diff_reg, channel_reg) begin if state = '1' then case spi_count is when "00000" => adc_mosi <= '1'; -- start bit when "00001" => adc_mosi <= sgl_diff_reg; when "00010" => adc_mosi <= channel_reg(2); when "00011" => adc_mosi <= channel_reg(1); when "00100" => adc_mosi <= channel_reg(0); when others => adc_mosi <= '0'; end case; else adc_mosi <= '0'; end if; end process; end behavioural; --much of the code is of credit to micronova electronics. For fifo, I use the Xilinx IP fifo generator with no FWFT working on 100Mhz clock both on write and read sides. FIFO width = 10 Depth = 2046 and tried increasing upto 131072 with no progress. This is my top level code with UART entity top_module is Generic ( PARITY_BIT : string := "none" -- type of parity ); port( clk, rst,trigger,diffn: in std_logic; adc_mosi,adc_clk,adc_cs : out std_logic; adc_miso : in std_logic; channel : in std_logic_vector ( 2 downto 0); wr_uart,uart_clk_en : in std_logic; WriteEn , ReadEn : in std_logic; full, empty : out std_logic; --w_data: in std_logic_vector(7 downto 0); Dout : inout std_logic_vector(9 downto 0); busy : out std_logic; tx,OutVal: out std_logic ); end top_module; architecture structural of top_module is signal fifo_data_out : STD_LOGIC_VECTOR (9 downto 0); component fifo is port ( reset_rtl_0 : in STD_LOGIC; clk_100MHz : in STD_LOGIC; full_0 : out STD_LOGIC; din_0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); wr_en_0 : in STD_LOGIC; empty_0 : out STD_LOGIC; dout_0 : out STD_LOGIC_VECTOR ( 9 downto 0 ); rd_en_0 : in STD_LOGIC ); end component fifo; begin MercuryADC : entity work.ADC port map ( clock => clk, trigger => trigger, diffn => diffn, channel => channel, -- data output Dout => Dout, OutVal => Outval, -- ADC connection adc_miso => adc_miso, adc_mosi => adc_mosi, adc_cs => adc_cs, adc_clk =>adc_clk ); fifo_i: component fifo port map ( clk_100MHz => clk, din_0(9 downto 0) => Dout(9 downto 0), dout_0(9 downto 0) => fifo_data_out(9 downto 0), empty_0 => empty, full_0 => full, rd_en_0 => ReadEn, reset_rtl_0 => rst, wr_en_0 => WriteEn ); uart_trx : entity work.UART_TX Port map ( CLK => clk, -- system clock RST => rst, -- high active synchronous reset -- UART INTERFACE UART_CLK_EN => uart_clk_en, -- oversampling (16x) UART clock enable UART_TXD => tx, -- serial transmit data -- USER DATA INPUT INTERFACE DATA_IN =>fifo_data_out (9 downto 2) , -- input data DATA_SEND => wr_uart,-- when DATA_SEND = 1, input data are valid and will be transmit BUSY => busy -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1 ); end structural; PFA the schematic of my design and waveform as well. input is 650 hz and Vpp= 1.5V; continuous sine wave. My output waveform appears to be distorted. I'm not sure if there has to be a delay incorporated while sampling the input signal or a is the issue between FIFO and UART. When WriteEn signal is asserted on FIFO, the full flag is asserted at the same instant, does that mean the size of FIFO is not enough. Kindly help, any inputs will be appreciated. MCP3008(3).pdf
  13. Hi all, I have the same symptoms as the OP posted here: I have been following tutorials, implementing simple designs like Adders, Shift-Registers etc. All was going fine until today when I implemented a Counter. The synthesis, implementation and bitstream generation succeeded, albeit with some warnings. When I flashed the FPGA, the 'program complete' LED lights up, and the 7-segment display is faintly lit. The project doesn't use the 7-seg, it displays the count in binary on the LED above the switches. The Info at the end of the programming says: INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. During synthesis, I also get the warning: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. ... even though I have a valid .xdc constraints file. So I went back to my earlier (working) examples, and after loading on to the FPGA, they give the same results and are no longer working. I downloaded the Basys3 GPIO example from Digilent and loaded that, and everything works fine (phew! I haven't blown the FPGA after 1 week!) All my internet searches bring me to a Xilinx page https://www.xilinx.com/support/answers/64764.html but I don't have a dbg_hub in my netlist as explained in the solution. Can anyone please help?
  14. Hello, I just opened my new basys3 board (novice EE student). As per the documentation I tried to power the board via usb-b (port j4) first through a laptop usb then through a 5v 2A charger making sure the jp2 jumper was set on usb and jp1 to the spi flash test program but the board did not turn on (not even the power good led). Trouble shooting that I performed: 1. Changed cable twice (didn't work) 2. Changed charger and usb ports (didn't work) 3. Powered board from external 5v power supply - the board worked perfectly. My question is could the smd soldering be defective, where can I mesure the voltage provided by the usb? Thank you for your help, If there is any more information I can provide please let me know
  15. I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  16. Hello, I'm trying to configure my Basys 3 board to control a DC motor through the Pmod connector with an HB5 within Vivado. I've followed all steps in the Pmod IP tutorial but I'm stuck at 3.3. I'm not sure which specific pmod ip block I should use or how exactly to connect it. I couldn't find one corresponding to the hb5. Any advice would be greatly appreciated. Additional points: I don't need clocks or interrupts fed to the pmod I'm simply trying to control the operation (on/off) of the motor through one of the on-board switches. Thanks, gd
  17. GabrielYamato

    Basys 3

    Hi all, I have some questions regarding Basys 3 Artix-7 FPGA Trainer Board. Is it possible to use Adept to program Basys 3 Artix-7? Is ISE 13.2 compatible with Basys 3 Artix-7? Thank you in advance,
  18. Hi, I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board. But the problem is that now it is not working for another three new Artix-7 Devices which I have bought just one month before. Same Verilog program is working in my previous three board but not working for the new three boards. Each operation, I have run 10 ring oscillator sequentially with each for 5s but after running one ring oscillator properly, then another ring oscillator has been gone to zero or sometimes not stop properly at the specific time. I have used the case statement to run individual ring oscillator. Please help me where is my main problem. I think in frequency counter function the clock from ring oscillator showing some problem but why is does not shown in other three FPGA board. The problem shows me very interesting but also painful to fix up it. Thanks
  19. NIcko

    BASYS3 programming...

    Hi - Simple programming - to get started with a BASYS3, do I need a JTAG cable or anything else other than a USB connection? Thanks
  20. How do I program the Quad SPI on the Basys3? The reference manual says it is possible from Vivado, but I am at a loss how to do it - IMPACT only detects the FPGA. On the Basys2 the process is pretty self-evident - Click the correct button in Adept, but what steps are required in IMPACT for the Basys3? Just a hint or a link would be great!
  21. zener

    Basys 3 D1-8 components

    Hello, I am trying to understand the protection mechanism of the I/O pins on the Basys 3, and would like more information about components D1-8 on the first page of the schematic. Could someone please tell me the part number? Best, Zen
  22. Hello I want to send an image from nexys4 DDR to basys3 through pmod. Is it possible? If yes then how to connect them. Nexys4 DDR will be master device.
  23. I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider code for the 7 seven of the basys3 by my instructor and I managed to do the stopwatch. When I changed all my constraints to the PMOD pins and connect to the external 7 segment I can see that it works because it stops and resets but it does the counting so quickly that I can't read at all. I am thinking that the problem may be because of the clock divider and the frequency of the clocks. The given code states that since the original clock of the basys3 is 100 MHz a counter will count up to 500000 to obtain a 100 hz and another counter will count up to 208334 that is 240 Hz. First of all I didn't understand why the second clock is 240 Hz and why do the counters count up to these irrelivant numbers. Secondly what can I do for the external 4 bit 7 segment to slow it down?
  24. Hi, I am trying to learn verilog and digital design using basys3 and vivado (webpack) tools. I implemented a jk flip flop using the following logic: module jk_flip_flop ( input [1:0] sw, input clk, input btnC, output reg [0:0] led); always @ (posedge clk) begin if (btnC == 1) led[0] = 0; else begin if (sw[0] == 1) begin if (sw[1] == 1) led[0] <= ~led[0]; else led[0] <= 1; end else begin if (sw[1]) led[0] <= 0; end end end endmodule What I see is when sw[0] and sw[1] are both 1 and if the previous led state was 1, the led does not turn off completely (it just gets dimmer). What could be the problem here, and how would I go about fixing it? I also tried using other LEDs on the board and each had the same problem. Thanks.
  25. Hello, I am attempting to communicate to a Pmod RF2: IEEE 802.15 RF Transceiver with a Basys3 board using the SPI protocol in VHDL. The microchip on the pmod is the MRF24J40. How do I identify the address of the MRF24J40? To my understanding, if I want to write/read a memory location on the MRF24J40, I need to send the address followed by the address of the specific memory location on the MRF24J40. Is it written on the microchip itself? The master and slave SPI modules that I am attempting to use are linked to this post. The documentation for the master and slave links are below. The specification sheets for the pmod and MRF24J40 are included as well. Master: https://eewiki.net/pages/viewpage.action?pageId=4096096#SerialPeripheralInterface(SPI)Master(VHDL)-Transactions Slave: https://eewiki.net/pages/viewpage.action?pageId=7569477 Pmod: https://www.digilentinc.com/Pmods/Digilent-Pmod_ Interface_Specification.pdf MRF24J40: http://ww1.microchip.com/downloads/en/DeviceDoc/39776C.pdf Thank you. spi_slave.vhd spi_master.vhd