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Found 27 results

  1. Hello all, Im new to this forum as well as new to the FPGA world. Currently i'm trying out a project that utilizes the Spartan 3e cp132 on the basys 2 to accelerate hash processing on my raspberry pi. I read somewhere that the basys 2's pmod host connector pins have 200 ohm resistors embedded to restrict current. Would it be fine for me to connect the digital spi pins of the RPI3 directly to the Pmod host pins of the basys or is the Pmod ACL2 required? In write up i read they directly connected to their fpga in similar projects but i wouldn't mind not destroying mine. Currently i have the pins attached to the JA slot except for the 3.3v wire. Directly connected:
  2. Hello, I'm making a project using Vivado, a Basys3 Atrix-7 FPGA Board and the PmodAMP2. The purpose of this project is to make a digital piano, but i can't find the proper code to send a specfic frequency to the Pmod AMP2 using VHDL and Vivado. Can someone help me out ? I'm pretty new to programming in VHDL. Thanks ! Robin
  3. Hello everyone... I'm new to this world and I bought a Basys2 a couple of years ago to use in my graduation. But I have never used it again since that time! Now I'm interested in discovering this world a bit more and the JTAG interface! Is it possible to write programs and load them into the FPGA board without having the ISE software?
  4. Louise

    BASYS2 - Adept testing

    I recently got my BASYS2 board. I installed the ISE Design Suite and Adept. I appear to have problems with the LEDs and the 4 buttons on the board. In Adept, when I run the test, I get the following issues. When I flip any of the last 4 switches (SW4 - SW7) on the board, on the screen the switch is shown correctly but the button below the flipped switch also darkens. Pressing any of the four buttons on the board has no effect on the screen buttons display. Is there something wrong with my board or is there something I need to do to fix this?
  5. Hi! My professor loaned to me their Digilent BASYS2 FPGA board. We wish to develop an FPGA-based Laser Remote Sensor (LIDAR) system. The BASYS2 will be triggered by the pulse driver of our Laser Diode. The Laser Diode pulses will be detected by a photomultiplier tube detector at selected rates and bin widths. We will connect the output (analog) of the photomultiplier tube to the BASYS2. How can we do this? Is it via the PMOD? Do we need an A/D converter like the PMOD AD1 or PMOD AD2? The BASYS2 has 4 PMODs with 6 pins each. Which PMOD (AD1 or AD2) is better for us? The AD1 has 6 pins only but has 2 channels while the AD2 has 12 pins and 4 channels (and is also half the price). If we buy the AD2, can we connect it to two PMODs in the BASYS2? Will this work? For another question, once the BASYS2 receives a trigger, the BASYS2 will read the PMOD to get the analog reading from the photomultiplier tube. How can we get the reading? Is it via the register address for that PMOD? Since this is digital, how can we know the voltage reading of the photomultiplier tube? Sorry for asking too many questions. Thanks in advance! Sincerely, Edgar Vallar
  6. Jan. 4, 2016 Hi! I want to use the Labview 2014 FPGA module to make a VI that uses the BASYS2 Digilent Board. The BASYS2 has the Spartan 3E-100 CP132 Xilinx FPGA chip. I will interface sensors to the BASYS2 and use the VI to get data automatically and process it. I already installed Labview 2014, Labview 2014 FPGA Module, Labview 2014 Realtime Module. However, I cannot find the BASYS2 (as a target) in the FPGA module and also in NI MAX. I found that Spartan 3E is part of the Xilinx University Program (XUP) and there is a Labview driver for it but it uses Labview 2012. Also, the Spartan 3E in the XUP that uses that Labview 2012 driver should be 500K. Can this driver also work with the BASYS2 board? Can someone give me an idea where to get a Labview driver for the Spartan 3E-100 CP132 (BASYS2 board)? I have emailed NI but they have no reply yet. Kindly email me or reply to this forum. Thank you. Edgar Email :
  7. I am a newbie, just bought BASYS2 digilent FPGA Board. I have background on microcontrollers. C/C++ is no problem for me. But I am having some trouble with FPGA. Actually, not with FPGA but with Compiler and ISE. As you can see in the attachment, I configured the FPGA chip. I am using BASYS2 board. This is the implementation code: --------------------- module myModule(A, B); input wire A; output wire B; assign B = !A; endmodule ---------------------- And this is the ucf code: ----------------------- # Onboard LEDs NET "B" LOC = "M11"; NET "A" LOC = "C11"; ------------------------ As boards technical sheet says, M11 is LED 1 and C11 is BTN 2. So I want LED to flash when I unpress the button. Do you see something wrong with the code? Because it aint working. If the code should have been working, what should I do? Am I skipping something? As you see I aldready generated programming file and run. So what next? Thanks.
  8. laltarac

    Basys2 PS/2 Keyboard

    Hello. Im working on a project that requires a ps2 keyboard to communicate to the Basys2 board. Does any one have any good links that might help me get started with this. Or, maybe would someone be able to post their Verilog code , if they've done it ? It would be much appreciated Thanks Liam
  9. Hi, I would like to buy Basys 2 together with NI multisim to save money. the site states that price for multisim is just 9.95 usd in case buy with basys2. Anybody know the way? Thank you. link:,66,1200&Prod=MULTISIM
  10. Hello. I found similar question “Working with DA4 PMOD on Nexys 4” posted on 23 Oct. 2014 and answer from JColvin. I understand the hint about usage of internal voltage. Nevertheless I don’t see output voltages. It is not easy to me to follow applied code, because I have learned so far Verilog and example is given in VHDL. I am electrical engineer and programmer by education, but I am new to digital electronics and FPGAs. I have acquired some initial experience by learning book “Digital Design Using Digilent FPGA Boards. Verilog/ Active –HDL Edition” by Richard E.Haskell and Darrin M.Hanna from 2012. I have implemented many examples from the book on BASYS2 board that I have. Now I would like to see voltages on outputs of PmodDA4 that I connect to my BASYS2 board. For beginning I will be satisfied with direct (permanent) voltages. I have been trying few versions of code and didn’t succeed. Please, advise – what is wrong? May be many things… I will try to describe my logic in details and attach my code too. I use Verilog. I connect PmodDA4 to JA connector of BASYS2 board. I have to create 3 correct signals: SYNC, DIN and SCLK. According to documentation I assume that: 1. SYNC: JA1 (B2) – pio<72> in ucf file. 2. DIN: JA2 (A3) – pio<73> in ucf file. 3. SCLK: JA4 (B5) – pio<75> in ucf file. Default frequency of a board is 50 MHz. I use half of this frequency – 25 MHz as a SCLK signal. I understand logic of operation so: if SYNC is high – data from signal DIN does not go into internal register of PmodDA4. After SYNC went low – data starts to go into internal register of PmodDA4. It goes into PmodDA4 on each negedge of SCLK and it counted by PmodDA4. By data we mean signal DIN: 0 or 1. After transferring 32 bits into internal register of PmodDA4 we have to change SYNC on high. May be that not necessarily to do right away after 32 accumulated bits, but I do that in my code, because in any way we must bring SYNC high for min 15 ns and after low for initiation of a new cycle of writing data into internal register of PmodDA4. I control that process by variable count. I simulated the process with Aldec simulator and visually it seems to me correct. I assume that bit db31 on a page 7 of is a first bit in time among 32 bits that is clocked into internal register of PmodDA4. Here is a sequence of 32 bits that I try to produce, taking JColvin’s notice about using Internal source of power. Don’t care bits db31, 30, 29, 28: 0000. Command bits db27, 26, 25, 24: 1011. Address bits db23, 22, 21, 20: 1111 – command for having voltage on all 8 outputs. For AD5628 12 bits db19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8 equal to 1 for max output voltage: 111111111111. And last 8 bits db7, 6, 5, 4, 3, 2, 1, 0: 00000001. As I understood your notice bits db27 and db0 have to be 1 – for using internal voltage as a source. My code for the project is attached in file Basys2_PmodDA4_code.txt. Basys2_PmodDA4_code.txt
  11. Hello everyone, I have met an issue when I use a generic counter and associate it when other component : my counter doesn't count. Firstly, I have designed three distinct function : a 2 bit counter, a multiplexer and one function allow to use 7 segment displays of Basys2. Then, I have associated these function in order to obtain one block diagram. The output of the counter are used to activate anode of 7 segment displays and they also used as input of 4 to 1 multiplexer. Finally the 4 to 1 multiplexer ptovide input for a block wich allow to light one of four 7 segement displays. When, I test only my 2 bit counter, it work correctly but when I associate this counter with other blocs diagramm, it doesn't count and stay to 0. I have tried to figure out but I haven't saw what's wrong with my design. This my vhdl code of my design : ------------------------------------------------------------------------------- -- -- Title : x7seg -- Design : Seven_Segment_Displays -- Author : Unknown -- Company : Unknown -- ------------------------------------------------------------------------------- -- -- File : C:\My_Designs\Example10\compile\x7seg.vhd -- Generated : Mon Jun 29 16:12:59 2015 -- From : C:\My_Designs\Example10\src\x7seg.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity x7seg is port( clk : in STD_LOGIC; clr : in STD_LOGIC; x : in STD_LOGIC_VECTOR(15 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0); an : out STD_LOGIC_VECTOR(3 downto 0) ); end x7seg; architecture x7seg of x7seg is ---- Component declarations ----- component counter_2 generic( N : INTEGER := 2 ); port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end component; component hex7seg_case_statement port ( x : in STD_LOGIC_VECTOR(3 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0) ); end component; component mux44 port ( s : in STD_LOGIC_VECTOR(1 downto 0); x : in STD_LOGIC_VECTOR(15 downto 0); z : out STD_LOGIC_VECTOR(3 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal nq0 : STD_LOGIC; signal nq1 : STD_LOGIC; signal digit : STD_LOGIC_VECTOR (3 downto 0); signal q : STD_LOGIC_VECTOR (1 downto 0); begin ---- Component instantiations ---- U1 : counter_2 port map( clk => clr, clr => clk, q => q( 1 downto 0 ) ); nq1 <= not(q(1)); nq0 <= not(q(0)); U2 : mux44 port map( s(0) => q(0), s(1) => q(1), x => x, z => digit ); U3 : hex7seg_case_statement port map( a_to_g => a_to_g, x => digit ); an(3) <= nq0 or nq1; an(2) <= q(0) or nq1; an(0) <= q(0) or q(1); an(1) <= nq0 or q(1); end x7seg;
  12. Hi everyone ! I need some help please : when I try to implement a counter in active HDL I have this warning message : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I explain : Firstly I have designed a basic counter with Basys2 board : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter_2 is generic (N : integer := 4); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter_2; --}} End of automatically maintained section architecture counter_2 of counter_2 is signal count: STD_LOGIC_VECTOR(N-1 downto 0); begin process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end counter_2; Then I have produced 24-bit (q(23) downto q(0)) clock divider, my goal is to divide original frequency and obtain 2.98 Hz in using q(23) as output of the clock divider : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity clkdiv2 is port( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end clkdiv2; --}} End of automatically maintained section architecture clkdiv2 of clkdiv2 is signal q: std_logic_vector(23 downto 0); begin process(clk, clr) begin if clr = '1' then q <= X"000000"; elsif clk 'event and clk = '1' then q <= q + 1; end if; end process; clk3 <= q(23); --clk48 <= q(19); --clk190 <= q(17); -- enter your statements here -- end clkdiv2; Finally I have used block diagram of the first counter and the clock divider to light the eight LEDs of Basys 2 as binary counter : ------------------------------------------------------------------------------- -- -- Title : count8_top -- Design : Counter -- Author : Unknown -- Company : Unknown -- ------------------------------------------------------------------------------- -- -- File : c:\My_Designs\Example8\compile\count8_top.vhd -- Generated : Mon Jun 15 22:01:20 2015 -- From : c:\My_Designs\Example8\src\count8_top.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity count8_top is port( clk : in STD_LOGIC; btn : in STD_LOGIC_VECTOR(3 to 3); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end count8_top; architecture count8_top of count8_top is ---- Component declarations ----- component clkdiv2 port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end component; component counter_2 generic( N : INTEGER := 8 ); port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal clk3 : STD_LOGIC; begin ---- Component instantiations ---- U1 : clkdiv2 port map( clk => clk, clk3 => clk3, clr => btn(3) ); U2 : counter_2 port map( clk => clk3, clr => btn(3), q => ld( 7 downto 0 ) ); end count8_top; Finally when I implement the block diagram corresponding to the code above, I have this warning : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I don't understand what does it mean. Could you help me please?
  13. xilinx_forever


    i have a pmod da2, i use it with basys2 board I use the refcomp design given by digilent, fixing the digitals values I simulate, and implement it on board, verified signal with digital analyser... put a scope on analog outputs... everything seams to be good, but no anlog value on the output! Some one could help me? thank you
  14. fefernandezpy


    Hi, I have PmodALS with basys 2. I need some example, in VHDL, to read data with the SPI protocol. I want to show the lectures on the 3 seven segments display of basys 2. thank you
  15. Does anyone use MultiSIM to program BASYS2? I teach an intro digital course that uses MultiSIM PLD Design to schematically program BASYS2 fpgas. I get a message when using ADEPT to upload that states: "Startup clock for this file is 'CCLK' instead of 'JTAG CLK.' Problems will likely occur. Associate config file with device anyway?" I can change this in Xilinx, but can't seem to in MultiSIM PLD. Any thoughts?
  16. Hello, I have successfully programmed my Basys2 using the 'djtgcfg' utility under Linux dozens of times, but I'm no longer able to do so. When I attempted to program the board yesterday, I got some unusual results: > djtgcfg enum Device: 3.....O......<. Product Name: Digilent Basys2-100 User Name: 3.....O......<. Serial Number: 210155528315 > djtgcfg init -d 'Basys2' ERROR: unable to open device "Basys2" > djtgcfg init -d '3.....O......<.' ERROR: unable to open device "3.....O......<." *I used the '.' character in the strings above to represent non-printable characters, because the replacement character used by my terminal won't display properly on this page. Using the product name or serial number yields a similar result. It appears that I can't communicate with the device due to a corrupted device ID. However, my computer has no trouble recognizing the Basys2 board: > lsusb ... Bus 003 Device 011: ID 1443:0007 Digilent Development board JTAG ...For what it's worth, here is the hexdump of the djtgcfg result above: > djtgcfg enum | xxd 0000000: 466f 756e 6420 3120 6465 7669 6365 2873 Found 1 device(s 0000010: 290a 0a44 6576 6963 653a 2033 fbbb b0df )..Device: 3.... 0000020: e04f a81f bdff bbf9 ec3c ad0a 2020 2020 .O.......<.. 0000030: 5072 6f64 7563 7420 4e61 6d65 3a20 2020 Product Name: 0000040: 4469 6769 6c65 6e74 2042 6173 7973 322d Digilent Basys2- 0000050: 3130 300a 2020 2020 5573 6572 204e 616d 100. User Nam 0000060: 653a 2020 2020 2020 33fb bbb0 dfe0 4fa8 e: 3.....O. 0000070: 1fbd ffbb f9ec 3cad 0a20 2020 2053 6572 ......<.. Ser 0000080: 6961 6c20 4e75 6d62 6572 3a20 2032 3130 ial Number: 210 0000090: 3135 3535 3238 3331 350a 155528315.So it appears the device ID as seen by djtgcfg is 33fb bbb0 dfe0 4fa8 1fbd ffbb f9ec 3cad 0aA couple of other details that might be helpful: I succesfully programmed a friend's Basys2 multiple times using djtgcfg after having this problem with my board. When using his board, the output from djtgcfg was normal (all printable characters).After experiencing this problem under Linux, I sucessfully programmed my Basys2 from a Windows machine. When using Adept2 under Windows, the device ID string still appears corrupted, but I am able to program it anyways. I don't have regular access to a Windows machine, so I'd really like to get this working under Linux again. I'm hoping this is just an issue of some corrupted Flash or EEPROM in the AT90USB that could be fixed by reprogramming it... but I'm not sure what to try next. Any ideas? Thanks for reading!
  17. Hi, I am trying to use the dpcutil.dll library with Visual .Net [C#]. I've managed to import the functions what I need to write and read registers in my BASYS2 EVB [250]. const string _dllLocation = "C:WindowsSystem32dpcutil.dll"; [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcInit(ref int perc); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern void DpcTerm(); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcGetDpcVersion(StringBuilder szVersion, ref int perc); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcOpenData(IntPtr phif, System.Text.StringBuilder szdvc, ref int perc, IntPtr ptrid); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcCloseData(IntPtr hif, ref int perc); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcPutReg(IntPtr hif, byte bAddr, byte bData, ref int perc, IntPtr ptrid); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcGetReg(IntPtr hif, byte bAddr, ref byte pbData, ref int perc, IntPtr ptrid);I know that I am using correctly the dll because I get the dll version from the function DpcGetDpcVersion(). My problem is when I try to use the funciton DpcOpenData. I got the error number 3103. I've read in the Digilent Port Communications Programmers Reference Manual that: ercCantConnect: 3103. Description: Can’t connect to communication module. First of all I've recored the rom flash of the BASYS2 with the reference design: In my DEV Visual .Net Application [C#]. I've been using the following steps: 1º.- DpcInit(ref theErc) -> theErc = 0 2º.- DpcGetDpcVersion(theVersion, ref theErc) -> theErc = 0 and theVersion =2.9.2 3º-. devCount = getDevCount() -> devCount = 2 4º.- for i= 0 to i < devCount => getDevName(i, devTemp); devTemp -> Basis2 AND devTemp -> Basis2_bis 5º.- DpcOpenData(hif, theDevice, ref theErc, ptrid) -> theErc = 3103 I am stacked in this step. Could you help me out how I can solve this problem? Thank you so much. Best regards.
  18. Hey every one! I use Basys2 board spartan3E 100k with Active HDL of ALDEC to study digital design. I have meet a problem when I try to implement my VHDL code the Implementation is ended and I have this message : "Warning: Implementation ended with warning(s)." In the Implementation report I have something like that : "ConstraintSystem - A target design object for the Locate constraint '<NET "an<3>" LOC = "k14";> [sw2led.ucf(37)]' could not be found and so the Locate constraint will be removed." I have tried to figure out but I don't know where the warning come from : my design is very easy , it consist just to turn on Led with slipe switch. I think the problem can come from ucf file but why? I have choose the ucf fitted to my design. Have you ever met this kind of problem? Help please!! I have attached my project if you want to see. Thanks
  19. Can we use Basys2 Pmods (GPIOs) for serial communication with outside world...? I want to implement a UART code on Basys2 board and want to use one of the Pmods (GPIOs) as Tx and Rx pins to establish a serial communication with outside world.. Can I do that..?
  20. Hello, Are the Basys 2 and the Basys 2 Spartan 3E FPGA boards the same?. Also, I saw you have a lot of labs of the Basys 2 board's requirement in both the Digilent website and the "Real Digital - A hands-on approach to digital design" text book. I would think if I buy the Basys 2 Spartan 3E FPGA board for my class at University of Calfornia at Irvine and use this FPGA board for the labs on your website and the text book "Real Digital - A hands-on approach to digital design". If I do this way, I can save cost for buying the FPGA board. Have the great holidays, Jonathan Tran
  21. meiyas

    Basys 3 With Ise Webpack

    Hi Can I use ISE webpack with the basys 3? I already have basys2 that I use with ISE webpack and was planning to buy basys3 now that I need more, but I wanted to know if I can continue to use the same software. I think you can't use vivaldo with basys2 but i can't find info if basys 3 can be used with the ISE webpack! Thanks!
  22. Hello, how can I implement this module using Verilog? And also, what is the meaning physical meaning of the 12 output bits of that module? Thanks in advance.
  23. Hello again I was looking at doing a servo project and bought a GWS-S03N servo motor and the HB3 PMOD. Looking at various sites, I have not seen anyone using the HB3 to control a servo. Is the only purpose of the HB3 to allow higher voltages to the servo motor than the Basys2 can output? It appears that pulse control is still coming directly from the FPGA board. So, if I used a higher voltage to the PMOD and motor, is there any chance of damaging the FPGA by connecting it directly to the control line of the servo? Is the HB3 more (or only) intended for driving standard DC motors and not servo motors? thanks
  24. Hi, I need help to initialise and implement an inout port in BASYS 2(Spartan 3E) FPGA board. I tried using IOBUF and assigned that port to B6 or A9 or C6.I couldn't get the result. Without using the IOBUF, i am getting the desired signal pattern as output but in milli volt range. And i'm not sure whether i able to recive or not with out using the IOBUF since I could not test it.. I want to implement the I2C protocol, so the sda line should be INOUT, which I cant figure out...Should I use any specific PIn in Pmods of Basys 2 as Inout port.... Please help me with this... Thanks in Advance Athul
  25. I've got a Nexys2 and a Basys2. I'd like to program them under Windows 8.1. From what I can tell, the only Xilinx software that's supported under Windows 8.1 does not support the Spartan 3E chips. Is there any way to program those chips from within Windows 8.1? Thanks, Keith