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Found 9 results

  1. Hello! For a (very modest) first try with the BASYS 3 board, I'd like to measure a signal using an ADC for the BASYS 3 board I have, possibly average the signal over a set of measurements and then send this out using PWM. I'm looking for examples in VHDL, and only found one in verilog so far. And any explanation that you care to offer me. As you can tell I'm a novis and a biologist at that. I've taken (75%) of a beginners course in VHDL, but am very interested and enthusiastic. Now, hit me (with kid gloves). Thanks in advance!
  2. Just some silly hello world code (I'm a super newbie to FPGAs) Vivado 2017.4, windows 7 xdc as per https://reference.digilentinc.com/learn/programmable-logic/doc/github/digilent-xdc => set_property IOSTANDARD LVCMOS33 [get_ports a] set_property IOSTANDARD LVCMOS33 [get_ports b] set_property IOSTANDARD LVCMOS33 [get_ports c] set_property PACKAGE_PIN U16 [get_ports c] set_property PACKAGE_PIN W19 [get_ports a] set_property PACKAGE_PIN T17 [get_ports b] vhdl=> library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_GATE is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end AND_GATE; architecture Behavioral of AND_GATE is begin c<= a AND b; end Behavioral; ============= Now, it runs just fine, but for some reason my Basys 3's LED 4 digit display is flickering like crazy, with a faint 8888. Is this a known issue? Am I missing something? Thanks
  3. Mell

    Vivado CLOCK_DEDICATED_ROUTE

    Hello everyone, I use 1 pin of the pmod connector of the basys3 board for receiving a signal. So in the .xdc file i set every right but I need to say that the incoming signal is not a clock. In the help it suggests "set_property CLOCK_DEDICATED_ROUTE value [get_nets net_name]". I changed the net_name with the signal name "set_property CLOCK_DEDICATED_ROUTE value [get_nets echo_pin]" but u get this critical warning "Invalid option 'FALSEecho_pin' specified for'objects'. anyone an idee? thank you
  4. Hello, I am attempting to communicate to a Pmod RF2: IEEE 802.15 RF Transceiver with a Basys3 board using the SPI protocol in VHDL. The microchip on the pmod is the MRF24J40. How do I identify the address of the MRF24J40? To my understanding, if I want to write/read a memory location on the MRF24J40, I need to send the address followed by the address of the specific memory location on the MRF24J40. Is it written on the microchip itself? The master and slave SPI modules that I am attempting to use are linked to this post. The documentation for the master and slave links are below. The specification sheets for the pmod and MRF24J40 are included as well. Master: https://eewiki.net/pages/viewpage.action?pageId=4096096#SerialPeripheralInterface(SPI)Master(VHDL)-Transactions Slave: https://eewiki.net/pages/viewpage.action?pageId=7569477 Pmod: https://www.digilentinc.com/Pmods/Digilent-Pmod_ Interface_Specification.pdf MRF24J40: http://ww1.microchip.com/downloads/en/DeviceDoc/39776C.pdf Thank you. spi_slave.vhd spi_master.vhd
  5. ikanip

    Questions on Artix-7 boards

    Hi, I am looking to buy a board of the Artix-7 family and trying to choose one between Arty, Basys 3 and Nexys 4 DDR. I have the following questions. 1. Is it true that the Vivado software that comes with Arty can only be used for one year since Arty is an evaluation board? 2. Is it possible to install the Vivado software on different computers and work on them (using the same board)? Does this behavior differ in any way among the three boards mentioned above? 3. I am confused about the number of cells in Nexys 4. On Digilent's website, it says Arty & Basys 3 both have about 33K logic "cells", and Nexys 4 has about 16K logic "slices". How many logic "cells" does Nexys 4 have? Which one of these boards can support a larger design? 4. Why does Basys 3 cost more than Arty even though it has less features (like no ethernet, etc.)? Looking forward to your response. This will help me to make a decision. Thank you! P.S.: I had earlier contacted Digilent through the "Contact US" link and asked these questions, but was told some of the questions were too technical, so I need to ask them in the forum. So please help!
  6. RS1

    Basys 3 not mapping corectly

    I have been working on a project with my Basys 3 board and recently ran into an issue where a 16 bit signal I mapped to the LED's was displaying on my seven segment display. The signal was generated by a sudo random number gen thats I created ( the signal changes with the event of the clock). My project also includes a segment decoder which does the appropriate time multiplexing to map a different signal to the segment display. Nowhere in my code can I find the reason for this incorrect mapping, so I wrote a dummy program that did nothing but take the random number and send the signal to the LED's ( I tried indexing the signal (ie. LED(0), LED(1) etc.) as well as creating a different signal for each LED) and still the signal was not showing up on the LED's but rather made the segment display show red faintly. When I send a constant signal to the LED's they light up correctly and the display remains off, why is this? and is there anything I can do to fix this issue and make this work. I need the seven segment display for another part of my project. RandGen_txt.txt TOP_txt.txt
  7. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth), as well as test benches for i2s_tx and Basys3_Abacus_top. All of these files are relatively simple. In addition, I've attached the constraint file, and an image of the output, taken with my DSO NANO V3. Furthermore, I've zipped up the entire project and uploaded here: https://drive.google.com/file/d/0B_8d0gTEx0yqaDFyOUhCTGU0QW8/view?usp=sharing Some thoughts: Maybe SSM2518 doesn't know to generate MCLK as 4xBCLK? Faulty chip? Anyways, if one of you has the time and energy to either point out flaws in my verilog or hardware setup, I would be very grateful. TIA oscillator.v i2s_tx.v sclk_div.v i2stx_tb.v Basys3_Master.xdc Basys3_Abacus_Top.v IMG_001.BMP
  8. Hi, I have a question about LEDs on the basys3 board. I'm using Verilog, and in my code I have a top level module which has other sub-modules within it. Like this: module top (); sub_module m1 (some_inputs, some_outputs); endmoduleIf I want to have the sub-module with an LED output, how would I go about doing it? I already tried having "output [15:0] led" in the definition of the top level module and also having it as an output of the sub level module, but that did not work. I also tried to simply declare led as a register within the sub_module, but that also didn't work.
  9. ricardo_lara_gomez

    Basys �

    I need a program to count the turns of a motor, could tell me I need?????????