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Found 23 results

  1. Hello, I am trying to interact with my Basys 3 board through the JTAG port on the board but I am not sure what cable to use with it. The cables listed for sale that I've seen, like the JTAG-HS2, say that they are not needed for Digilent FPGA boards. Is there a cable that is intended for use with the FPGA boards? Thanks, Seth
  2. Good day, We are having a number of students who have accidently broken off the micro USB connector from the Basys 3 board. Do you have a suitable sub part number for this connector J4 ? Thanks, John
  3. Please confirm if the Basys 3 Artix-7 FPGA Trainer Board is supported by the Vivado System Generator on Simulink®.
  4. Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display the image. summary of code functionality: Divide main 100 MHz clock by four to get 25 MHz clock (required pixel frequency) , establish VGA synchronization and display the image on a 640 x 480 resolution @ 60 Hz. The code is shown below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity vga_driver is Port ( clk : in STD_LOGIC; --100 MHz main clock. Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; R,G,B : out STD_LOGIC_VECTOR (3 downto 0)); end vga_driver; architecture Behavioral of vga_driver is signal DFlipFlopOut1: STD_LOGIC; signal DFlipFlopOut1_NOT: STD_LOGIC; signal ClockDiv4: STD_LOGIC; -- 25 MHz Clock signal ClockDiv4_NOT: STD_LOGIC; constant picture_size : Integer:=90000; -- 300 Pixels* 300 Pixels picture= 90000 Pixels --Signals for Block RAM signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0):="0"; signal addra : STD_LOGIC_VECTOR(16 DOWNTO 0):=(others=>'0'); signal dina : STD_LOGIC_VECTOR(11 DOWNTO 0):=(others=>'0'); signal douta : STD_LOGIC_VECTOR(11 DOWNTO 0):=(others=>'0'); constant HD : integer := 639; -- 639 Horizontal Display (640) constant HFP : integer := 16; -- 16 Right border (front porch) constant HSP : integer := 96; -- 96 Sync pulse (Retrace) constant HBP : integer := 48; -- 48 Left boarder (back porch) constant VD : integer := 479; -- 479 Vertical Display (480) constant VFP : integer := 10; -- 10 Right border (front porch) constant VSP : integer := 2; -- 2 Sync pulse (Retrace) constant VBP : integer := 33; -- 33 Left boarder (back porch) signal hPos : integer := 0; signal vPos : integer := 0; signal videoOn : std_logic := '0'; component RisingEdge_DFlipFlop is port( Q : out std_logic; Clk :in std_logic; D :in std_logic ); end component ; component Picture_Block_RAM is PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); end component; begin DFlipFlopOut1_NOT<=not DFlipFlopOut1; ClockDiv4_NOT<= not ClockDiv4; --Pass Main 100 MHz clock to 2 cascaded DFlipFLops to divide frequency by 4. Result frequency= 25 MHz. U1: RisingEdge_DFlipFlop Port map (clk=> clk, D=> DFlipFlopOut1_NOT, Q=>DFlipFlopOut1); U2: RisingEdge_DFlipFlop Port map (clk=> DFlipFlopOut1, D=> ClockDiv4_NOT, Q=>ClockDiv4); --Block RAM containing picture U3: Picture_Block_RAM Port map (clka=>ClockDiv4, wea=>wea, addra=>addra, dina=>dina, douta=>douta); Horizontal_position_counter:process(ClockDiv4) begin if(ClockDiv4'event and ClockDiv4 = '1')then if (hPos = (HD + HFP + HSP + HBP)) then hPos <= 0; else hPos <= hPos + 1; end if; end if; end process; Vertical_position_counter:process(ClockDiv4, hPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(hPos = (HD + HFP + HSP + HBP))then if (vPos = (VD + VFP + VSP + VBP)) then vPos <= 0; else vPos <= vPos + 1; end if; end if; end if; end process; Horizontal_Synchronisation:process(ClockDiv4, hPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if((hPos <= (HD + HFP)) OR (hPos > HD + HFP + HSP))then HSYNC <= '1'; else HSYNC <= '0'; end if; end if; end process; Vertical_Synchronisation:process(ClockDiv4, vPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if((vPos <= (VD + VFP)) OR (vPos > VD + VFP + VSP))then VSYNC <= '1'; else VSYNC <= '0'; end if; end if; end process; video_on:process(ClockDiv4, hPos, vPos) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(hPos <= HD and vPos <= VD)then videoOn <= '1'; else videoOn <= '0'; end if; end if; end process; draw:process(ClockDiv4, hPos, vPos, videoOn) begin if(ClockDiv4'event and ClockDiv4 = '1')then if(videoOn = '1')then if (unsigned(addra)<picture_size) then R<=douta(11 downto 8); G<=douta(7 downto 4); B<=douta(3 downto 0); addra<=STD_LOGIC_VECTOR(unsigned(addra)+1); else R<=(others=>'0');G<=(others=>'0');B<=(others=>'0'); end if; else R<=(others=>'0');G<=(others=>'0');B<=(others=>'0'); addra<=(others=>'0'); end if; end if; end process; end Behavioral; My problem is that the image does not display as expected. I get this displayed on my screen: As you see, there are 2 problems immediately noticed. 1st: The image is not the same, obviously. 2nd: The image should not take the whole display since it is 300 * 300 pixels while the resolution is 640*480 pixels meaning that some data is being repeated without intention. The default display of BASYS 3 is this. I am putting this just for reference so you can know how my screen displays 640*480 resolution: I tested the VHDL code by printing colors on my screen by direct output assignment and it works as intended. So the problem is probably with accessing the block RAM. A snippet from my .coe file: MEMORY_INITIALIZATION_RADIX=2; MEMORY_INITIALIZATION_VECTOR= 011101010100, 010101110111, 000110011111, 010110101100, 000110111111, 001000100010, 001000100010, 001000100010, 001000100011, 000101100100, 100110100001, 111011010110, 111110110110, 111110000101, 111110010100, : : --it goes on and on until last line, line number 90002, 90000 since 300*300 pixels= 90000. The added two is due to the first 2 lines. : : 101100100010; I am stuck at this point. Where could the problem be?
  5. I have connected an ov 7670 camera to my Basys 3 board and want to transmit the frame to a PC via the micro-usb port. I have tried UART serial communication, but the bit per second rate is simply not high enough to transmit a full 640 * 480 frame 15/30 times a second. I had the idea of implementing some sort of parallel communication, however I could not find any information or guides. I was wondering if anyone could help me out either with parallel communication, or suggesting a different method of transmitting frames to a PC. Thanks in advance.
  6. Hi everyone, I am trying to connect an OV 7670 camera to my basys 3 board and program it so that it shows the live camera feed on a monitor connected to the VGA port of the basys 3. The only thing I was able to do is connect the camera to the pins on the basys 3. I've looked everywhere, including here, but cannot write the other components, like frame buffer, myself. I would appreciate any help or any suggestions about where to look for help. P.S. I have enough knowledge of VHDL and the basys 3 board to implement an adder that uses the 7-segment display. Thanks.
  7. I've coded UART receiver and transmitter separately in verilog and tested them on Basys 3 FPGA board with Tera Term terminal. I want to connect a USB Keyboard with the board and on pressing keys on keyboard, they gets reflected on Tera Term at same time. ToDo: Basys 3 Board receives data from keyboard and then transmits that data to elsewhere (say Tera Term terminal or a Pmod LCD screen) Problem:- Can anyone help me in how to use USB Keyboard with Basys 3 and how can I implement my UART in this. Attechments: UART receiver and transmitter code is attached below. UART_tx.v UART_Rx.v
  8. this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  9. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  10. thweight

    Hello Everyone!

    I just received my BASYS 3 board and everything is going normally for me. I can't seem to find which cable I need in order to program it from my PC. Anyone know the answer?
  11. I have a switch on my Basys 3 board that the board thinks is always in the on position. Does anyone have any ideas for troubleshooting the issue. I've put a multimeter to it to test continuity and it behaves like you would expect. I know that it's something to do with the switch and not whatever output I display to (it does the same for the LED's, the seven segment display, and through the SDK terminal on my computer.
  12. Hi i am unable to blink led using PMOD connector. i have used PMOD Ip as GPIO.
  13. Arduino is the SPI Master and therefore provides the clock, SPICLK through a PMOD. How do I receive the clock in a good way on the FPGA? Vivado does not approve of checking rising_edge(SPICLK) so I though I'd put a clock buffer or something in between (not that I know why or what they do but it sounds like a good idea). At some point Vivado told me to add "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SPICLK_IBUF}]" to the constraints file, but I still got warnings and it didn't recommend I proceed. If I have the top level SPICLK connected to an IBUF_IBUFDISABLE with the disable line connected to the slave select (SS) line, I get this warning: [DRC 23-20] Rule violation (CKLD-2) Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads - Clock net spi_buf is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): IBUF_IBUFDISABLE_inst/O If I have the top level SPICLK connected to an IBUF_IBUFDISABLE and that into a BUFGCE, with the disable line connected to the slave select (SS) line and the inverse of SS into the CE, I get this warning: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. IBUF_IBUFDISABLE_inst (IBUF_IBUFDISABLE.O) is locked to IOB_X0Y25 and BUFGCE_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 Roughly the same warning was issued with just the BUFGCE. I know there are other ways of polling the input clock from the arduino and treating it as normal signal but I want to do it the "proper" way.
  14. Hey everybody, I am ready to start learning, but I have had a really hard time with a previous board and now it seems I have a curse of doubt on my shoulders... I will not give up but I could use a boost. I just need to know what I need to do to use a Basys 3 trainer board on a 64bit windows 10 machine (step by step). I'm not in school, my friends could care less about this stuff, and the professors I have contacted have not returned my emails. Pitiful, I know, and I don't like it. Bring me some joy through your patience, Please. I'm really excited, just really tiered and underwhelmed. The last board I had offered very little support. I am glad that with diligent there appears to be a community and hope to be part of the fun and tears. Best, JMP
  15. bakytzhan

    Divide a clock signal

    Hello everybody! Guys, I wanted to ask How to do a seconds, minutes signal with Basys 3 ? How can I delay a 100 Mhz clock?
  16. andrei

    basys 3 ila performance

    Hello, As I can see, the basys 3 locked Vivaldo license allows for the use of the ILA (Integrated Logic Analyzer) IP core; artix 7 also shows as a supported fpga family on http://www.xilinx.com/products/intellectual-property/ila.html Looking over Xilinx's ILA documentation (http://www.xilinx.com/support/documentation/ip_documentation/ila/v5_0/pg172-ila.pdf) resource utilization section, it seems the ILA uses quite a bit of logic fabric (though the data is from a Kintex 7 fpga and I don't know how big the resource usage difference is between this family and the artix 7). Have any of you successfully used the ILA with the basys 3, and if so, how much of the fpga was occupied by it? Thank you
  17. In this project, the instructor / educator in the target countries will use Basys 3 to teach digital systems. The object of the project. To change the theoretical type of learning in Ukraine, Georgia and Armenia to practice-oriented competence-based approach. To speed up integration between Higher Educational Institutes and business in target countries. To establish cooperation between EU and target countries in education and research. http://www.tempus-desire.eu/
  18. Hi everyone! I'm Jorge an Electronics Engineer who want to buy the Basys 3 FPGA for the first time. I took some FPGA subjects at the University and I did some practical stuff using a Spartan 3 FPGA and Nexys 2 through ISE design suite. Now I want to have my own FPGA to continue learning myself and do some crazy stuff. Basys 3 description sais that it is not supported by xillinx ISE, so the only possibility is to use it through Vivado. My big doubt is: should I buy the 'Vivado Design Suite Voucher' together with the FPGA?? It is only 10$ difference. What is the difference between buy it or no? Can I generate the bytestream in Vivado without having the voucher? Finally, if I buy the 'Vivado Design Suite Voucher', when does the license finish? Should I buy 2 vouchers? Is it posible to use Vivado Voucher license in 2 pcs? my home pc and my laptop. Thanks for the help, I'm still quite new with this kind of programs and licenses. Up to now we used the ISE web pack. Regards
  19. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?
  20. Greetings Digilent Staff, I recently bought a Basys 3 to use in a VLSI Desgin course of my university (Cal State Long Beach). I did all the steps on the video tutorial you guys posted on youtube to upload my first project to the board. However, in the "synthesis" part, I keep getting this error, even though I already acquireda license: "[Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7a35t'. Please run the Vivado License Manager for assistance in determiningwhich features and devices are licensed for your system."What should I do? Since I am only doing simple projects, I did not think it would be necessary to buy the$10 key for the Vivado software. Should I do that? What can I do now? Thank you very much for your attention.
  21. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE. http://m.instructables.com/id/How-to-use-Verilog-and-Basys-3-to-do-3-bit-binary-/
  22. Hi how is the file (license) to lock the Vivado baysis3 sent? I got the confirmation i ordered it. The order file says it is the only email? Does this come from Xilinix? I can't find anywhere the website or the forum telling me how i am to obtain the code license or what ever? I have downloaded 15.1 but I don't know what to do next. My Basys 3 board arrives Monday. I would like to have the software ready to get started. Thanks Rex
  23. Clint from WSU has posted some projects based on Vivado. User can use Basys 3 or Nexys 4 and develop the project in Vivado. http://www.eecs.wsu.edu/~ee214/projects.php