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  1. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <
  2. this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  3. Arduino is the SPI Master and therefore provides the clock, SPICLK through a PMOD. How do I receive the clock in a good way on the FPGA? Vivado does not approve of checking rising_edge(SPICLK) so I though I'd put a clock buffer or something in between (not that I know why or what they do but it sounds like a good idea). At some point Vivado told me to add "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SPICLK_IBUF}]" to the constraints file, but I still got warnings and it didn't recommend I proceed. If I have the top level SPICLK connected to an IBUF_IBUFDISABLE with the
  4. Hi Guys I am trying to communicate with my Basys 3 board using USB-UART Bridge (Serial Port) and TeraTerm software but with no success. the weird part is that my device is recognizable by the Hardware Manager of Vivado and i can send the bitstream file successufly to program my FPGA but it is not showing up in the Hardware Manager of Win7 as seen in the attached cut out, so i dont know which COM Port is connetected to (if that's the case ) to be able to communicate with my board serially. I tried installing FTDI FT2232HQ USB-UART bridge driver from but didn't solve my pr
  5. I am having layers of problems with the Pmod MicroSD. My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. Issues: [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7] I get this error for 4 pins set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t] set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t] set_property BOAR
  6. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my blo
  7. Tells me PmodWIFI is packaged with board value arty and to update my basys3 to the arty. I am confused. Well hang on a second. It finished generating a bitstream and I see no critical warnings in the project summary. In fact if I tell vivado to discard user generated messages in the messages window, the project has no indication of critical warnings at all. Still confused but closer to my goal.
  8. Using Windows 10, my Basys 3 Artix-7 FPGA Trainer Board will not power on. Bought a new USB cable from Digilent and the board still did not power on.
  9. Hello, I am a fairly new to using the Basys 3 and a student using it for a project. I am attempting to output 4 separate variables from the Pmod ports on the board using the JA Pmod part. When I run synthesis, implementation, and then bitstream, I get the same error for all but one of my outputs. My error message: [Common 17-69] Command failed: Site cannot be assigned to more than one port ["D:/LogicLab/SignalsProjectMK1/SignalsProjectMK1.srcs/constrs_1/new/BasysOut.xdc":16] Constraint: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk]
  10. Hello, I am trying to interact with my Basys 3 board through the JTAG port on the board but I am not sure what cable to use with it. The cables listed for sale that I've seen, like the JTAG-HS2, say that they are not needed for Digilent FPGA boards. Is there a cable that is intended for use with the FPGA boards? Thanks, Seth
  11. Good day, We are having a number of students who have accidently broken off the micro USB connector from the Basys 3 board. Do you have a suitable sub part number for this connector J4 ? Thanks, John
  12. Please confirm if the Basys 3 Artix-7 FPGA Trainer Board is supported by the Vivado System Generator on Simulink®.
  13. Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display
  14. I have connected an ov 7670 camera to my Basys 3 board and want to transmit the frame to a PC via the micro-usb port. I have tried UART serial communication, but the bit per second rate is simply not high enough to transmit a full 640 * 480 frame 15/30 times a second. I had the idea of implementing some sort of parallel communication, however I could not find any information or guides. I was wondering if anyone could help me out either with parallel communication, or suggesting a different method of transmitting frames to a PC. Thanks in advance.
  15. Hi everyone, I am trying to connect an OV 7670 camera to my basys 3 board and program it so that it shows the live camera feed on a monitor connected to the VGA port of the basys 3. The only thing I was able to do is connect the camera to the pins on the basys 3. I've looked everywhere, including here, but cannot write the other components, like frame buffer, myself. I would appreciate any help or any suggestions about where to look for help. P.S. I have enough knowledge of VHDL and the basys 3 board to implement an adder that uses the 7-segment display. Thanks.
  16. I've coded UART receiver and transmitter separately in verilog and tested them on Basys 3 FPGA board with Tera Term terminal. I want to connect a USB Keyboard with the board and on pressing keys on keyboard, they gets reflected on Tera Term at same time. ToDo: Basys 3 Board receives data from keyboard and then transmits that data to elsewhere (say Tera Term terminal or a Pmod LCD screen) Problem:- Can anyone help me in how to use USB Keyboard with Basys 3 and how can I implement my UART in this. Attechments: UART receiver and transmitter code is attached below.
  17. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different k
  18. thweight

    Hello Everyone!

    I just received my BASYS 3 board and everything is going normally for me. I can't seem to find which cable I need in order to program it from my PC. Anyone know the answer?
  19. I have a switch on my Basys 3 board that the board thinks is always in the on position. Does anyone have any ideas for troubleshooting the issue. I've put a multimeter to it to test continuity and it behaves like you would expect. I know that it's something to do with the switch and not whatever output I display to (it does the same for the LED's, the seven segment display, and through the SDK terminal on my computer.
  20. Hi i am unable to blink led using PMOD connector. i have used PMOD Ip as GPIO.
  21. Hey everybody, I am ready to start learning, but I have had a really hard time with a previous board and now it seems I have a curse of doubt on my shoulders... I will not give up but I could use a boost. I just need to know what I need to do to use a Basys 3 trainer board on a 64bit windows 10 machine (step by step). I'm not in school, my friends could care less about this stuff, and the professors I have contacted have not returned my emails. Pitiful, I know, and I don't like it. Bring me some joy through your patience, Please. I'm really excited, just really tiered a
  22. Hello everybody! Guys, I wanted to ask How to do a seconds, minutes signal with Basys 3 ? How can I delay a 100 Mhz clock?
  23. Hello, As I can see, the basys 3 locked Vivaldo license allows for the use of the ILA (Integrated Logic Analyzer) IP core; artix 7 also shows as a supported fpga family on Looking over Xilinx's ILA documentation ( resource utilization section, it seems the ILA uses quite a bit of logic fabric (though the data is from a Kintex 7 fpga and I don't know how big the resource usage difference is between this family and the artix 7). Have any
  24. In this project, the instructor / educator in the target countries will use Basys 3 to teach digital systems. The object of the project. To change the theoretical type of learning in Ukraine, Georgia and Armenia to practice-oriented competence-based approach. To speed up integration between Higher Educational Institutes and business in target countries. To establish cooperation between EU and target countries in education and research.
  25. Hi everyone! I'm Jorge an Electronics Engineer who want to buy the Basys 3 FPGA for the first time. I took some FPGA subjects at the University and I did some practical stuff using a Spartan 3 FPGA and Nexys 2 through ISE design suite. Now I want to have my own FPGA to continue learning myself and do some crazy stuff. Basys 3 description sais that it is not supported by xillinx ISE, so the only possibility is to use it through Vivado. My big doubt is: should I buy the 'Vivado Design Suite Voucher' together with the FPGA?? It is only 10$ difference. What is the difference between buy