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Found 3 results

  1. Hi, I have noticed an issue in a bare-metal application when polling the register XUARTPS_ISR (Channel Interrupt Status Register). No issues when I use XUART_SR (Channel Status Register) instead. The issue: When I poll XUART_ISR for TX_FULL and RX_EMPTY the UART interface becomes an unstable state. No sending and receiving after a few bytes is possible. Has somebody noticed the same issue or can somebody explain whats happening? Edit: My current code for the UART interface (Here I use XUARTPS_SR instead. But when I poll XUARTPS_ISR (0x14) it doesn't work.): #include <string.h> #include <dev/io.h> #define UART0_BASE 0xE0000000 #define UART1_BASE 0xE0001000 #define UART_CR_OFFSET 0x0 #define UART_CR_RXRST 0 #define UART_CR_TXRST 1 #define UART_CR_RXEN 2 #define UART_CR_RXDIS 3 #define UART_CR_TXEN 4 #define UART_CR_TXDIS 5 #define UART_MR_OFFSET 0x4 #define UART_IER_OFFSET 0x8 #define UART_BGEN_OFFSET 0x18 #define UART_SR_OFFSET 0x2C #define UART_SR_RXEMPT 1 #define UART_SR_RXFULL 2 #define UART_SR_TXEMPT 3 #define UART_SR_TXFULL 4 #define UART_FIFO_OFFSET 0x30 #define UART_BDIV_OFFSET 0x34 struct uart_reg { unsigned int cr; unsigned int mr; unsigned int ier; unsigned int bgen; unsigned int sr; unsigned int fifo; unsigned int bdiv; }; static struct uart_reg regs; void uart_init(void) { unsigned int tmp; regs.cr = (UART1_BASE + UART_CR_OFFSET); regs.mr = (UART1_BASE + UART_MR_OFFSET); regs.ier = (UART1_BASE + UART_IER_OFFSET); regs.bgen = (UART1_BASE + UART_BGEN_OFFSET); regs.sr = (UART1_BASE + UART_SR_OFFSET); regs.fifo = (UART1_BASE + UART_FIFO_OFFSET); regs.bdiv = (UART1_BASE + UART_BDIV_OFFSET); /* Check if RX/TX is enabled */ tmp = io_rd32(regs.cr); /* Skip init if RX/TX enabled */ if (tmp & ((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN))) return; /* Reset RX/TX paths */ tmp = io_rd32(regs.cr); tmp |= ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST)); io_wr32(regs.cr, tmp); do tmp = io_rd32(regs.cr); while (tmp & ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST))); /* Set baudrate to 115200; UART Reference Clock: 100MHz */ io_wr32(regs.bgen, 124); io_wr32(regs.bdiv, 6); /* Set mode: 8 Databit, 1 Stopbit, No Parity */ io_wr32(regs.mr, 0x20); /* Enable RX/TX */ tmp = io_rd32(regs.cr); tmp &= ~((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN)); io_wr32(regs.cr, tmp); } int uart_send(unsigned char *buf, int len) { int i; unsigned int tmp; for (i = 0; i < len; i++) { do tmp = io_rd32(regs.sr); while (tmp & (1 << UART_SR_TXFULL)); io_wr08(regs.fifo, buf[i]); } return len; } int uart_recv(unsigned char *buf, int len) { int i; int ret = 0; unsigned int tmp; tmp = io_rd32(regs.sr); if (tmp & (1 << UART_SR_RXEMPT)) return 0; for (i = 0; i < len; i++) { buf[i] = io_rd08(regs.fifo); ret++; tmp = io_rd32(regs.sr); if (tmp & (1 << UART_SR_RXEMPT)) return ret; } return ret; }
  2. vic

    Running XAPP1079 on Zybo

    Hi, I'm trying to run the XAPP 1079 on Zybo. As the profile is not originally made for this specific board, I had to make some changes. I follow all the insructions for the Vivado and the SDK, but in the end after the board boots from the microSD card I don't see anything in the terminal. I was wondering first if the changes that I made are correct and if anymore are needed. One specific issue I am having is that while creating an instance of the Zynq7 processor, it uses the configuration preset for the ZC702 board. Can/Should I change that? Below are the tcl scripts that i have modified. I have tried running the profile both on the 2017.1 and the 2015.4 version of Vivado. It is possible that it has something to do with the standalone bsp. I have tried running a simple hello world from a single core of the ARM A9 and it runs just fine. But when I try running a simple hello world application with both the cores (essentially changing the SDK part of the XAPP), I still see nothing on the terminal.
  3. vic

    Running XAPP1093 on Zybo

    I am trying to run something akin to the Xilinx 1093 profile. I want to have bare-metal apllications on both the ARM A9 and the Microblaze co-processor. In the SDK, I created a Zynq FSBL and three separate simple Hello World application projects, for CPU0, CPU1 and Microblaze. When I debug the application, I download all three of these projects to the FPGA. But I only see a Hello World from Microblaze and CPU1 on the terminal. If I don't download the CPU1 project, then I can see the Microblaze and CPU0 Hello Worlds just fine. I have attached the tcl script for the block design I used. As far as the application projects, they are the simple auto-generated hello world .c files from the SDK. What prevents CPU0 from sending Hello World to the terminal when the project for CPU1 is also downloaded? My end goal is to run either an image processing or an encryption algorithm, that divides tasks between the two cores and Microblaze or the ARM processor in general and Microblaze. 1) Should something change or be added to the block design for this to happen? 2) Is the communication between ARM and MB achieved through functions in the .c files? design_1.tcl