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Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to ILA directly? If it is possible only with AXI interface, so I will deeply study the AXI4 referance manuals. Many thanks...
Hi, Does anyone know if/where I can find an AXI4 example running on Atlys similar in functionnality to the HDMI PLB demo ? The example would show how to read frames from HDMI in, store to memory via AXI4 VDMA core, and read from memory to HDMI out. Thanx !
Hello, dear FPGA enthusiasts! Currently, I have been working with my OV7670 camera and can present it on an HDMI screen. However, this was done without a simulation. What I want to do right now is to use a TPG provided from Xlinix in my design and remove the OV7670 fully. However, the problem is that I really don't know how to go next since I am using uB together with a VDMA and TPG. I know that you can include the ELF file from the uB in order to simulate your design together with uB. My question to you is where I can find C code for the TPG used in the nexys video board? Is there any guidelines or documents that provide information on how I have to set up my design before I simulate AXI4 peripherals. Do I need to create my own testbench or is there testbench's out there that are already done? Initially, I was using the ILA to test my peripherals but that is a very ineffective way of testing my models since it takes a lot of time and it is hectic to recompile when I make a small change. I have attached my block design. regards, John hdmi.pdf
Hello, I downloaded the source HDL for a h.264 decoder from opencores.org. I'm trying to integrate this core into a video pipeline using the Zybo board. In order to use this core, I need it to be on the AXI4 bus. I'm trying to package the IP as an AXI4 peripheral using the Create and Package IP wizard, however I get errors. I've searched the Xilinx documentation for help as to what these might mean, buy I haven't found anything super helpful. My Questions: 1. Is it possible to package this core as an AXI4 peripheral? 2. Can anyone explain, or point me to some documentation that can help me understand the errors shown in the picture image1? Thank you, Jason