Search the Community

Showing results for tags 'axi'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 15 results

  1. Hi, On my Arty A7 board i have the hello world running with Microblaze and UART. I added from the board tab the 4 buttons then i added the 4 LEDs. I'm using 2020.1, and by default it combined the AXI GPIO so there is a dual channel GPIO where both the leds and the buttons are connected. My problem is, that in Vitis the generated IO example code uses the same port, and only the buttons work... the device gets configured as such in the code: #define GPIO_OUTPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define GPIO_INPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID In xparameters.h i fou
  2. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  3. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When lo
  4. I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: I have a Video Test Pattern Generator connected to an Axi4-stream to Video Out IP driven by a Video Timing Controller IP. Here is a 100 ms simulation for the circuit: Vsync does not get generated, so clearly there is something wrong with this circuit. All examples I have found online include a MicroBlaze or Zynq processor with their design connected to the V
  5. Hello All, I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples. I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the
  6. jello_cat

    Arty with custom IP

    I have Arty A7-35T and I tried following this tutorial (http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html) to have the Microblaze communicate with custom VHDL. In the C++ file the macro for 'XPAR_MY_MULTIPLIER_0_S00_AXI_BASEADDR' matches what the address editor says. I always 0 from the address that should be the result of the multiplier. I don't know what I'm doing wrong or if anything from the tutorial needs to be done different for the Microblaze.
  7. hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  8. Hello, I am trying to create an IP that reorders AXI DRAM addresses, similar to the one described in Xilinx xapp792. The main purpose is to change from Row/Bank/Column to Bank/Row/Column addressing. A portion of the block design where the IP will be used is attached. When I create this IP, it gets its own address space. However, it should only be a forwarder, like the axi interconnect. I know I should be setting some parameters in IP packager, but I don't know what those are. Can anyone help me out with this? Thanks, Rajat Rao
  9. Hi, I'm new to FPGAs and I have trouble finding documentation. In particular: How exactly VSync and HSync is handled for HDMI input? What can I assume about them? I'd like to create a AXI Master to store input in DDR. However I cannot find a reference for AXI4M_bus_port - how is timing handled for write_burst? Are there any guaranteed on ordering of stores through AXI Master to DDR? Matt
  10. Hi everyone, I'm trying to use the axi_dma xilinx driver in order to make transfer between PS and PL in both way. I posted this issue on the xilinx forum but I didn't get any response. This is the link: https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-DMA-test-err... Now I'm using the version 2016.3 for both software, Vivado and Peralinux. Any idea?? I have looked for across the web but I cannot be able to manage the axidma engine. Thanks in advance Best,
  11. hello friends, can we write to the block memory generator through port A by axi interface and read to the same block memory generator through port B by native interface???
  12. I am trying to create an interrupt handler using Zynq. I am using the Zybo board and am using the Linux kernel from the following link: https://github.com/Xilinx/linux-xlnx.git. I have searched the Internet and I think I have everything set up properly but my handler never gets called in my driver. Here is my block design: ... and my interrupts set up in vivado: My dts file (attached here) contains the following: ps7_gpio_0: [email protected] { #gpio-cells = <2>; clocks = <&clkc 42>; compatible = "xlnx,zynq-gpio-1.0"; emio-gpio-width = <64>
  13. Hi: I was wondering if anyone has used the MicBlaze - AXI based access to the XADC to communicate with the AUX4 (XSM_CH_AUX4??) and AUX12 (XSM_CH_AUX12??) channels. Based on my read of the XADCdemo.sv and the comments, I guess the CMOD A7 analog inputs to be the XSM_CH_AUX 4 and 12 channels. I seem to be missing something with regards to how to initialize them. Thoughts? Peter
  14. Hello; have any of you guys had any experience with axi_perf_mon IP core? can you refer me to a help or tutorial of it?
  15. Hi, Does anyone have ever sent data to AXI interfaces without using /dev/mem in Petalinux? I'm curious. I'm sure there is a way but I don't know how and I don't want to use a pointer that opens /dev/mem. I want to send a lot of data to several AXI components in the same time and I think using /dev/mem will give some problem. Thanks for your response.