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Showing results for tags 'axi traffic generator'.
1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits. 2)I want to enable my axi traffic gen, on start bit from the axi gpio and write the data into the axi register which is on the slave side?? kindly help me I'm beginner to vivado model based design. i have build design as per the image attached on addition to this, i want to add the above features to it as