Search the Community
Showing results for tags 'axi memory mapped master'.
Hi, I want to create an AXI Memory Mapped Master from a custom IP which can read/write off-chip memory. I would like to use this IP in my Vivado block design. Target platform is: Nexys4DDR board with xc7a100tcsg324-1 FPGA. I use Vivado 2014.4 under Win7 64 bit. I have made the Gettig started with Microblaze guide (https://reference.digilentinc.com/nexys4-ddr:gsmb). Everything went fine, now I have a Vivado block design with Microblaze, Uart, MIG, and some other peripherals. I have also set the master.xdc file, and I can generate the bitfile. SDK template tests (hello world, memory test) als