Search the Community

Showing results for tags 'axi memory mapped master'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 1 result

  1. Hi, I want to create an AXI Memory Mapped Master from a custom IP which can read/write off-chip memory. I would like to use this IP in my Vivado block design. Target platform is: Nexys4DDR board with xc7a100tcsg324-1 FPGA. I use Vivado 2014.4 under Win7 64 bit. I have made the Gettig started with Microblaze guide (https://reference.digilentinc.com/nexys4-ddr:gsmb). Everything went fine, now I have a Vivado block design with Microblaze, Uart, MIG, and some other peripherals. I have also set the master.xdc file, and I can generate the bitfile. SDK template tests (hello world, memory test) also passed successfully. I have a custom made IP, from which I would like to make an AXI MM Master peripheral, and I want to control (read/write) the DDR2 memory from my custom made IP. I have created a new AXI4 peripheral with the Create or Package IP wizard in Vivado. I have choosen the following interface: Interface Type: Full Interface Mode: Master Data Width (Bits): 32 After clicking Finish, Vivado creates a new peripheral in which I can intantiate my custom IP. However this generated myip_v1_0_M00_AXI.vhd looks a little bit hard to understand for me. I haven't even find any Read/Write ports amongst the interface ports. Basically what do I need to control from my custom IP? I assume the M_AXI_AWADDR, M_AXI_WDATA, M_AXI_ARADDR and M_AXI_RDATA ports for address and data, but what about read/write etc? I have found tons of tutorials on the web about how to make an AXI Lite Slave interfaced IP, but I couldn't find any reference designs for AXI Memory Mapped Master. Could you please post me some examples or helping by making comments in my file attached? Thanks! Shodan