Search the Community

Showing results for tags 'axi gpio'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 1 result

  1. 1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits. 2)I want to enable my axi traffic gen, on start bit from the axi gpio and write the data into the axi register which is on the slave side?? kindly help me I'm beginner to vivado model based design. i have build design as per the image attached on addition to this, i want to add the above features to it as