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Showing results for tags 'axi dma'.
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Hi, I have been familiarizing myself with VHDL and FPGAs in general with the Digilent Basys3 board. Recently I have tried incorporating the Microblaze in to my design just to familiarize myself with it. I have created a simple block diagram where I connect a custom AXI-stream counter to an AXI-DMA block. The counter just streams incrementing numbers and adds the tlast signal to generate frames. My purpose is to develop a minimum working example on AXI-DMA transfer. I plan to transfer x-number of samples generated by the AXI-stream counter with the AXI-DMA to a BRAM memory. On programming the AXI-DMA core I have followed the Xilinx manual PG021 https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf section Direct Register Mode (Simple DMA) on page 71. Initializing the DMA works. However, after sending the transfer command to the DMA no transaction happens. I wonder whether the problem is in my C-code or the block diagram. I have verified with the vivado ILA that the counter is working and produces a stream of data. In addition I have tied tkeep port to logical high on the s2mm port on the DMA. Is it possible I have forgotten something else? Any suggestions will be warmly welcomed. top_module.pdfAXI_DMA_minimum_example.c
Hi, I'm doing a project that uses AXI DMA. I already done my Ip Core, my Block Design e and my SDK code. The problem is that when my program reaches while(XAxiDma_Busy(&axiDma, XAXIDMA_DMA_TO_DEVICE)) it gets stuck. I'm using a Zedboard and Vivado 2017.4. I did a search, found out that it's a very popular problem, but I had no success solving it, so I'm posting here trying to get more help. I'm attaching my sources. Thank you srcs.zip
Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. https://github.com/mstuehn/dma_proxy Any help is appreciates Best regards,