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Found 2 results

  1. Hi, I have integrated simplex TX aurora block and simplex RX aurora blocks into a single design through a loop-back in order to make duplex mode. But while simulating the XSDK codes, TX length and RX length are mismatched. I am working with Kintex development DAQ board [xc7k160tffg676-2], and i have attached the BD design in which TX and RX are make into external. Where i am going wrong i don`t know, please point out and guide me. Please find the attachment of BD diagram. Thanks
  2. Are you interested in trying out a 10.8 Gbps 4-lane data interface on your Genesys2 board? Try spending some time in Transceiver Boot Camp. You won't be disappointed. TransceiverBootcamp.zip