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  1. tara901

    USB audio on PYNQ-Z1

    Hi there, I am pretty new to using the pynq-z1 board. I wish to do some audio recording via a usb microphone! I am struggling with doing this successfully, is anyone able to help me with this? I am getting "no soundcards found" when issuing alsa commands arecord -l and aplay -l. I understand pynq -z1 receives audio samples as PWM or PDM, but im not sure exactly what that means in terms of linux drivers available. any help would be appreciated! Thanks
  2. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  3. Hi, I am trying to establish a lowpass filter to Audio Demo code of Nexys A7 board. I have implemented a filter however i hear just a noise. If you share your time, i will be happy. I have added the project which was generated by Vivado 2018.2. Vivado Project Best regards.
  4. hello, I am new to designing with pmod wifi. I want to send audio files from pc to the zybo via pmod wifi and then process it then play it via output port. is it as easy as that example showed here? Bests, Meysam Sh.
  5. Hello, I'm working on an audio project with a Zybo Z7-10 board (with Vivado 2016.4), and as a starting point I'm trying to set it up as an audio passthrough. I've been working off of the DMA audio demo, but I can't seem to get it to output a continuous stream. Is there a way to modify it so that the sound input can be immediately routed to the output without having to record it first?
  6. Hi, I am trying to implement Audio Demo on Zybo Z7 using this: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-dma-audio-demo/start First, I wanted to do it just using Vivado 2018.2 (without SDK). I followed what is described in this comment: Bitstream is succesfully generated with two following warnings: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado
  7. Hi, I have been following tutorials from Zynq book for Zybo Z7 board. In tutorial 5, where the zybo_audio_ctrl IP core is used, I can not get any audio data through my board. The tutorials are made for Zybo board, and I followed migration guide (to Zybo Z7), but still no success. Any help would be appreciated. Thanks
  8. I am trying to access the audio codec SSM2603 on ZYBO over i2c interface from linux user-space for some register get and set, what i did so far I enabled in the device-tree PS I2C_0 in system-user.dtsi &i2c0 { ssm2603: [email protected]{ #sound-dai-cells = <0>; compatible = "adi,ssm2603"; reg = <0x1a>; }; i2cdetect -l output i2c-1 i2c Cadence I2C at e0004000 I2C adapter i suppose i2c coec should appear on address 0x1a but nothing i2cdetect -y -r 1 0 1 2
  9. Hello, I have a question about audio. I've already asked about the issue. Another question is "Known Issues" of the BSP provided in "github". (https://github.com/Digilent/Petalinux-Zybo-Z7-10/blob/v2017.2-1/README.md) What does "Audio is currently completely non-functional" mean in "Known Issues"? Does "Zybo Z7-10" mean it is impossible to run audio properly? Do you provide a BSP that solves this problem? We did not have to buy the "Zybo Z7-10" if Audio was not supported. I would appreciate your help in more depth. Regards,
  10. Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]),
  11. hi im running a spectrum on an audio amplifier, i cant seem to get lower noise than circa -70-75db im i doing something wrong or is this the lowest i can expect?
  12. Hello everyone! I am broadcast audio engineer (ex Harman Pro/Studer) with decent experience of complex audio/control systems and DIY enthusiast with Arduino and Raspberry type-of-toy knowledge:) I also can code PHP (Yii/Laravel), a bit of Python and .NET (WPF, Core and Web Forms). Component level repairs were more of a childhood game, but smell of flux was always somewhere near.. This time i have a goal to get familiar with FPGA world, so here I am and immediately starting a new thread regarding my project:) Cheers!
  13. I want to be able to output a .wav file. I can output a sine wave just fine from python, but I'm having trouble with this. I am loading the wav file. The array is populated. I've been looking for a funcPlay example, but I have not found any. I am able to import the file into waveforms and send it out using play. Thanks. import numpy as np import scipy.io.wavfile import matplotlib.pyplot as plt import ctypes import winsound from ctypes import * import time from dwfconstants import * import sys rate, data = scipy.io.wavfile.read('/Users/don/1.wav') plt.plot(data) plt.show() s
  14. I am doing a project with some audio DSP. For this I am using the audio codec on the Zybo. The first thing I want to do, is to be able to record and playback audio with a little delay between input and output. In order to speed up the development process, I decided to use the DMA Audio demo. But I'm lacking some information or rather some documentation. So is there any of your guys who knows which registers is references to here (Audio controller registers) in the code below. Since I2S is an hardware interface standard, so there should not be any registers. So I think it has something to do wi
  15. Hi, I recently purchased a Zybo board and used the DMA Audio Demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start) to acquire audio input and output. The Audio codec records 5 seconds of audio and then passes it to the Zynq PL via I²S protocol, that is it transmits the bit clock BCLK, the word select RECLRC and the data recorded RECDAT. My goal is to take this data and apply a filter on it, before the stream is mapped into memory with a DMA and then sent back to the audio codec and played in earphones. But I don't really understand how th
  16. Hi! I've hooked up a CMOD-A7 to an audio codec board designed for the Raspberry Pi, getting ready to play with some audio. You can find the VHDL source at http://hamsterworks.co.nz/mediawiki/index.php/STGL5000#sgtl5000_interface.vhd It is still rough and ready, but it works
  17. Hi Guys, im realatively new to electronics and even newer to measurements! I've just got my discovery 2 and was hoping someone might be able to guide me with some general question and tips. Sorry if my questions sound stupid in advance very new!!! Firstly, measuring balanced connections? I know what's required to measure single ended audio connections but trying to work out how best to measure seeing have inverting and non inverting connections plus gnd? Can anyone provide some guidance on how to go about this? Assume I know nothing when it comes to oscilloscope and wavefor
  18. I am trying to determine if and how a Vivado IP Core can be used to create and audible tone. I have been reviewing the DSS Compiler 6.0 product guide and simulation tutorial ug937. I have configured it as shown in the attached image. I understand the sine wave output should be bits (10 downto 0) of "m_axis_data_tdata". It is asking for s_axis_phase_tvalid, s_axis_phase_tdata for input. I cannot seem to get a clear understanding of what these are. Can someone explain in layman's terms? I also created a clock divider to drop aclk down to 12kHz as an attempt the get my sine wave into t
  19. This is a response question to an earlier thread that I was not able to continue. I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. "ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8" I've tried it with 6, 8 and even all 32-bits and I get the same failure. Code: inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phas
  20. Is it possible to connect the PmodAMP2 board to active (amplified) speakers? From the schematic I see that the "sleeve" connector of the audio jack is connected to "OUT+" of the amplifier IC and not to GND as an active speaker might require.
  21. I recently purchased the Zybo, zynq development board, along with a MIC3 so that I could hopefully take in audio from the PMOD port and then process it in Arm processor, and finally output it through the audio output port. I'm having trouble getting the audio routed with the IP in vivado. I'm fairly new to the vivado IP integrator but I have some experience creating verilog projects. Has anyone used the MIC3 with the zybo, or know how to get the audio from a MIC3 in one of the PMOD ports, into the ARM for proccessing? Any help would be greatly appreciated.
  22. akashvakil

    zybo audio

    Hi, I was trying to get started with ZYBO audio. I have followed steps as seen in tutorial. I am using Vivado 2016.2 as prescribed. But when I run the TCLfiles I have the following errors.: ERROR: [IP_Flow 19-3461] Value 'hdmi_in_ddc' is out of the range for parameter 'IIC Board Interface(IIC_BOARD_INTERFACE)' for BD Cell 'axi_iic_0' . Valid values are - Custom INFO: [IP_Flow 19-3438] Customization errors found on 'axi_iic_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier err
  23. I am working on a school project making a sound (tone/ multi-tone) generator using a BASYS3 and Vivado. I am having trouble getting the sound part out. As a test I wrote a simple VHDL program to create a 357Hz square wave. I declared an output bit 'dataout'. I ran a simulation using Aldec-HDL Student Edition and I am getting the output squareware. I am using the PmodAMP2 connected to JB1 top row. In my xdc file I have dataout assigned to A14 ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {dataout}] set_property IOSTANDARD LVCMOS33 [get_ports {dataout}
  24. Hello guys; Can you refer me to a quick guide about how to use Audio signal on ZYbo board? I just want to know if there is any simple tutorial about how to get data from audio jack and have in on Arm side. Appreciate your comments in advance.
  25. Hi everyone, I have seen discussion on this topic already in previous posts, but I am hoping someone has made a little progress and just hasn't posted yet. I'm hoping to be able to play audio (SFX & music) in a pong game I've made with Zybo. Does anyone have tips/experience on how to achieve this? FYI: I have an SD card, so that would be an option for audio file storage. Thanks for your time and effort! I am enjoying Zybo immensely so far. -Josh