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  1. This is my third post for my Soundbox project. I have sucessfully created a sinewave output from the DDS Compiler 6.0. I am running the Vivado Simulator and the m_axis_data_tdata shows a nice smooth wave. I have it set for analog waveform with radix as signed decimal. I have a PulseWidth Modulator process set to output to a single bit, but have been getting un-predicted results. I setup and attached the PMODR2R 8-bit digital to analog converter to see what the actual signal looks like. I have then attached my oscilloscope to the analog output. I have been getting un-predicted output on my scope. I was playing with the simulator and stumbled upon the output I am getting on my scope. It appears to be the "unsigned decimal" output. How can I correct this? How can I get the "signed" analog output from my BASYS3 PMODR2R? Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wave_top is port (clk, swt, rst :in std_logic; analogout: out std_logic_vector(7 downto 0); dataout, senb: out std_logic ); end Wave_top; architecture Behavioral of Wave_top is signal clkdiv: std_logic; signal cntr: std_logic_vector(31 downto 0); signal PWM_IN: std_logic_vector(7 downto 0); signal PWM_ACC: std_logic_vector(8 downto 0):= (others => '0'); signal PWM_OUT: std_logic; signal tvalid: std_logic; signal m_axis_data_tvalid : STD_LOGIC; signal m_axis_data_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0); COMPONENT dds_compiler_0 PORT ( aclk : IN STD_LOGIC; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; begin senb <= swt; tvalid <= swt; DIVIDER:process(clk, rst) begin if rst = '1' then cntr <= (others=> '0'); else if (rising_edge(clk)) then cntr <= cntr + 1; end if; end if; end process; clkdiv <= cntr(13); inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => tvalid, s_axis_phase_tdata => cntr(20 downto 13), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); PWM_IN <= m_axis_data_tdata(7 downto 0); PWM:process(clkdiv,PWM_IN) begin if rising_edge(clkdiv) then PWM_ACC <= ("0" & PWM_ACC(7 downto 0)) + ("0" & PWM_IN); end if; end process; dataout <= PWM_ACC(8); analogout <= PWM_IN; end Behavioral;