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Found 49 results

  1. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! 😃 Question 1 (solved): I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000. If I look at the MPMC configuration, its base address parameter is set to 0x48000000. I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ? Question 2 (pending): The output signal is 1280x720 with a pixel clock at 75 MHz which is not fully HDMI compliant. Some receivers get along with this signal but some unfortunately don't. To get a "true" 720p signal, pixel clock should be 74.25 MHz. Is there any way I could modify the clock generator to get this 74.25 MHz clock signal ? Thank you very much for your help
  2. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  3. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The only downside for Version 1 is that you need a Digilent ATLYS board to serve as the test platform. [Edited] Not 4 hours have passed and I found a silly bug that mis-reported packet size. I've replaced the archive. I also forgot to add the teaser: Wed Oct 17 16:13:03 2018 test_interval_reg = 0x000000000100 >>> Starting test Payload Size = 65536 Total Number of TEST Packets sent = 60000 Total Number of TEST Packets received = 60000 Total Number of TEST Bytes sent = 3932160000 Total Number of TEST Bytes received = 3932160000 Total Number of Errors = 0 Total Number of PHY rxerr Events = 0 Total Duration of the test (in Seconds) = 31.585437952 Percentage Errors = 0.0 TEST packets sent per second = 1899.60956347 Tx Data Rate (Bytes/s) = 124492812.352 Rx Data Rate (Bytes/s) = 124492812.352
  4. Hi, my ATLYS baord is not detected by an operating system any more as valid USB device when connected to the PROG mirco usb port. On linux i see for example: [85564.500749] usb 2-1.2: new high-speed USB device number 80 using ehci-pci [85579.582195] usb 2-1.2: device descriptor read/64, error -110 [85594.764710] usb 2-1.2: device descriptor read/64, error -110 I played now a little bit with it, and are pritty convinced that the content of the EEPROM for the FX2 is damaged. Sadly i cannot find a copy of the eeprom content for atlys on the internet. I actuallys found one from an nexys 2 board and when i flash this with the FX2 software on the eeprom, the atlys is recogniced again even with adept, but this old version does not seem to support all features needed by a reacent adept. I mean i can configure my bitfiles, but when i try to flash them, adept tells me that the communication with the FPGA failed. So is there somewhere the firmware of an ATLYS FX2 availiable, so i can recover my ATLYS properly? Cheers Dennis
  5. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that there is a Multiplexer which is deciding the clock for either 100 or 1000 Mbps mode. The select line of this MUX is 'speedis10100_int'. I tied this signal (speedis10100_int) to an LED and found that this select line is not changing on changing the Switch (1000 to 100 Mbps). I further tried driving this select line of MUX manually by a Slide switch. Then I can observe the clock (output of MUX) changing from 125 Mhz to 25 Mhz (when i slide the switch and change the network switch to 100mbps). But still the address swap example doesn't work at 100 Mbps. Inputs of the MUX are 1) 125 Mhz generated by clock generator and, 2) mii_tx_clk (25 Mhz coming from PHY) Thanks in advance. Deepak Verma
  6. Hi FPGA gurus ! I am facing trouble while trying to attach my Atlys USB JTAG device to a Centos 6 virtualbox VM. I recently had no choice but to upgrade my computer from Windows 7 to Windows 10. As a Windows 10 version of ISE 14.7 was available, I decided I could do the upgrade before realizing that ISE 14.7 for Windows 10 was indeed ISE 14.7 for Linux running a VirtualBox... Nevermind. The problem is that it seems I can't attach Digilent USB JTAG to the VirtualBox. Here is my configuration : Windows 10 Pro VirtualBox 5.2.8 (I upgraded it so that I could install Extensions to enable USB 2 and USB 3 support) Adept2 is installed on Windows 10 and works fine, Atlys board is recognized and I can run the test application OK. Now, here is my problem : Let's turn on the computer first and do a fresh test ! Atlys Board is attached to USB ports (JTAG and UART) but is turned off. VirtualBox USB configuration is configured as shown in USB_parameters.jpg Now, let's turn VM on, Atlys board still off. The attachable USB device list in VB is shown in USB_devices_atlys_off.jpg As you can see, neither JTAG nor UART devices are listed, which is expected as Atlys board is off. Now, let's turn the Atlys board on and see if the listing has changed... It has ! as shown in USB_devices_atlys_on_1.jpg Also, you can see in Device_mgr.jpg that Windows has no driver problem with JTAG and UART devices. You may notice UART device is automatically attached. Looking at /dev/tty* shows that the UART device is now available through /dev/ttyACM0 as shown in TTY_devices.jpg Let's have a look at the JTAG device status (USB_devices_atlys_on_2.jpg), it reads "captured", whatever that means ... Now, let's try attaching it... It raises an error with message shown in Digilent_USB_JTAG_attachment_error.jpg "USB device is busy with a previous request" :/ This is sad ... Of course, no other device appears in /dev/tty* Greping dmesg for FTDI pattern returns Nothing. Only UART USB devices appears in dmesg log... I've tried the same test with USB 3 (xHCI) configuration selected. Do any of you have an idea on how I could attach the USB Digilent JTAG device to my Centos 6 VirtualBox machine ? Any help will be highly appreciated. Thanx a lot. Cheers
  7. Hi, Does anyone know if/where I can find an AXI4 example running on Atlys similar in functionnality to the HDMI PLB demo ? The example would show how to read frames from HDMI in, store to memory via AXI4 VDMA core, and read from memory to HDMI out. Thanx !
  8. Hi, In the atlys_rm_v2 doc page 14, it is mentioned " An EDK reference design available on the Digilent website (and included as a part of the User Demo) displays a gradient color bar on an HDMI-connected monitor", however I cannot find this project in the resource center, would you please give me this project ? Thanks in advance,
  9. I downloaded the demo project of configuring SPI flash and DDR2 memories controllers from this link, I would like to use the two controllers for my own application, the problem is the project is not associated with a documentation that explains the steps required for testing the peripherals of the system, can you please guide of how to test the two components mnetioned above ?
  10. Hi, I am trying to use the videotiming controller provided in the VmodCam demo project to display static images on an HDMI screen, my problem is that the size of images used is different from the rersolution selected by the controller, can I modify the code to add a new resolution ?
  11. Hi, Could you please explain how the read and write batches are used in the frame buffer controller ?
  12. Hi everyone, I've been reading Xilinx's DS643 pdf on MPMC configuration (v6.06.a). Table 91 page 170 lists the maximum frequency that can be used for the VFBC interface clocks, VFBC_Cmd_Clk, VFBC_Wd_Clk and VFBC_Rd_Clk. Only Spartan-3A DSP, Virtex-4 and Virtex-5 devices are listed. Where can I find the maximum frequency that can be used to clock VFBC on Atlys spartan-6 ? Thanx a lot, cheers.
  13. Hi FPGA gurus ! I'm trying to achieve video processing with Atlys board. My goal is to real-time rotate some VGA Stream ([email protected]) form hdmi input to 720p hdmi output. Rotation is 90° clockwise. The attached picture sketches what i'm aiming at. I've been thinking of using HDMI Demo project for this. I am a total noob to all this FPGA thing, i'm slowy trying to learn but it's not that simple when you don't know anything about electronics =) From what I have understood, in the HDMI demo the frame in written to DDR2 memory with a single call to the VFBC. TMDS data is pushed in the FIFO and when a new frame is detected, then the Write Command is emitted and stores the whole frame to memory. I thouht a good design for my project would be to store line by line, configuring the VFBC command with X=1, Y=639 and BaseAdress = [(40*lineStride)+(1160-lineCnt)] * 2. This way : line 1 (blue) is stored in the frame buffer as a 1 pixel wide column starting at pixel (1159,40) line 2 (green) is stored in the frame buffer as a 1 pixel wide column starting at pixel (1158,40) ... line 640 (orange) is stored in the frame buffer as a 1 pixel wide column starting at pixel (680,40) My understanding of the HDMI Demo is that modifying user_logic.vhd in hdmi_in is all i have to do, so that instead of writing the whole frame in one vfbc command, the frame should be written line by line with 640 VFBC commands, one for each line, with constant width = 1, constant height = 639 and baseAdress computed as shown above. Is this correct ? Any Suggestion, hint, advice or help will be highly appreciated as I quite lost with this !! Cheers
  14. Hi I'm trying to transmit digital signals through a cable. In orther to avoid noise, I am using a differential output (LVDS) to transmit the information from the FPGA to a Cable. At the end of the cable, I'm using a converter to convert the differential signal to a single-end signal (LVDS to Single End converter). For that I need to feed my converter circuit through pin 6 of pmod connector (pin6 = vcc pin = 3.3V). Initially everything was working properly. However the other day, I switched on the board again (Atlys Board) and checked that I no longer have vcc on pin 6 (pin6 = vcc pin = 0V). Can anyone explain what's going on? Is the board damaged?
  15. Hi all FPGA fans and gurus ! First off : I am a total noob at all those FPGA and electronics things. So please be patient with me Now, for my problem : I recently got a second hand Atlys Board. My goal is to program it so that it can realtime rotate some hdmi input to its output. The input is a [email protected] signal. The goal is to rotate it and output a [email protected] signal (640 pixels fit in 720, with black borders 40 pixels wide each side). So, as I don't know anything about FPGA programming, I downloaded the following EDK HDMI demo on the Atlys resource page, I thought it would be a good start to understand how hdmi inputs and outputs work with the Atlys board : To build the project, I'm using ISE 14.7, fresh install (Windows 7). Actually I can build the project and program the Atlys with it, and even run it. However it seems it doesn't work OK. I looks like there are problem with interrupts, especially with the push buttons on the board. Wichever button I push, the callback function is never called. However, I have evidence the program does run. If, for instance, I change the main function to make it draw thing on the screen, it does it. I can also print things in the virtual terminal of the SDK. For instance, if I do a xil_printf at the beginnig of main(), things print in the terminal. However If I put a xil_printf at the beginning of the button handler function, whichever button i press nothing prints ... reason why I think it might be an interrupt problem. Needless to say that Adept button test is OK. Other thing : I'm using a fresh ISE 14.7 out-of-the-box install. I don't know if specific add-ons need installing to make Atlys work flawlessly with EDK. I might have missed some things. Especially, on the Atlys Resource page on Digilent's website, there is a zip archive and the following comment : "Atlys board support files for EDK BSB wizard. Supports EDK 13.2 - 14.7 for both AXI and PLB buses." Do I need this ? I don't have a clue about what BSB wizard is... I think all has been said =) Thanks in advance to all helpers ! Cheers
  16. Zygot goes back to the future to transfer data between two FPGA boards at 600 MB/s. Along the way he has a debugging adventure, learns ( AGAIN!!! ) why free stuff rarely is free and remembers when Digilent made FPGA boards that were great for development projects. This is a nice project for beginners or old hands to read through even if you don't have the hardware. CAUTION!!! You must read through the README text file before trying to replicate this project in hardware. Release 2 fixes some bad commentary in the source files and improves the behaviour of the UART transmitter
  17. Hi, I recently purchased the pmodbt2 bluetooth interface module and tried interfacing it with the Atlys board. I used the GPIO demo bit file which was given in the forum for verification (after modifying it), but I was not able to see the output in the terminal software (Teraterm). I followed the instructions given in the demo, but I was not able to see the output; are there any specific changes I need to make in the module or in the terminal software? Can someone help me out with this? Ishan
  18. Hi, For a project, I want to align two input HDMI video sources in Atlys Spartan 6. I want to implement an asynchronous FIFO which will synchronize video source B with video source A timings (picture attached). However, the FIFO should be of the size to store atleast 8 MB (frame size of each video source = 1920*1080*32 bits). How to implement this asynchronous FIFO in Atlys Spartan 6? My atlys kit has MIRA P3R1GE4JGF DDR2 IC on it instead of Micron MT47H64M16xx-25E which is in older boards of Atlys Spartan 6. I am using ISE Design Suite 14.2 and running Xapp495. The frame rate that I am working on is 120 FPS and resolution is 1080p. The pixel speed is 146.3616Mhz. If possible, then share some sample code which can be modified to implement this FIFO. Thanking you in anticipation.
  19. Hi Jon, I am trying to use the ISE demo project that configures VmodCam video feeds at resolution 1600x900 using HDMI port, I made the following modifications: - Fist of all, I removed the framebuffer controller of DDR2 and replace by a BRAM controller. - I am trying to read one frame from camera A and sending it to pc through UART, I Implemented an RGB-to-grayscale converter in order to minimize the memory usage 3 times. Each time I store 1600 bytes in the BRAM and then sends them through the UART transmitting interface, however there is a big difference between the data transfer rate of the VDHCI connector used to connect VmodCam to atlys board and the maximum data transfer rate of the UART protocol which is 115200 bps, my question which parameter in the camera should I control to ensure correct reading of data, and can I use the video capture mode to take one frame of the video feed, In the manual there is a mention of FIFO in the camera, how many pixels can the fifo store, and finally can I take the videtiming controller out of the desing ? Thank you very much, TE SAIDI
  20. I want to build an Audio Processor using Diligent Atlys. I want to know whether is it practically realizable??? I don't have dedicated faculty in my college due to which i will require help . Has anyone done it in the past so that he or she could help me or guide me if i could get stuck???
  21. Hi everybody, Could someone please give a brief explanation how the DDR2 in the Atlys demo projects work for video buffering at a resolution of 1600 x1200 30 fps, I got confused in the VHDL code ? Thank you, TK SAIDI
  22. Hi guys, Actually this is my first post in this forum, could you please provide me with some guidlines of how to implement HDMI controller on genesys board starting from the Atlys's one ? peace,
  23. Hi I am a new user, just trying to setup the digilent Atlys board, in Windows 10 with ISE 14.5 I have installed the UART driver "XR21V1410" from EXAR. But Adept 2 doesn't detect the board at all. (No device connected) I am using the programing UART port with a USB cable for connecting the board to pc. Thanks for your help in advance