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  1. Hi, I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed. To achevieve this goal, I designed a self made pcore to act as a clock generator. This "720p compliant clock generator" pcore is a simple vhdl/mpd file. Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE. The idea was to replace the original clock generator of the design with this core. Instead of delivering 600Mhz and 75MHz outputs, it del
  2. Hi, I've written a simple vhdl core to act as an EDID emulator. It's basically a PLB Master core, catching interrupts from a PLB Slave XPS_IIC core attached to HDMI SDA/SCL line to manage I2C/DDC protocole. This core works fine when xps_iic is connected to J3:IN I2C ports (M16 for SCL, M18 for SDA). However, nothing happens when the xps_iic is connected to J1:IN I2C ports (C13 for SCL, A13 for SDA). I guess I'm missing something with JP2 and JP4 jumpers. Can you please tell me the correct jumper settings to have J1:IN hdmi port act the same way as J3:IN ? Please note tha
  3. Dear all Please help in accessing ethernet port of Atlys FPGA board. Is it possible to access ethernet port using available IP in ISE or I have to write protocol for it. please reply if anybody has done that. -- Gopal krishna
  4. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! 😃 Question 1 (solved): I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride
  5. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  6. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The
  7. Hi, my ATLYS baord is not detected by an operating system any more as valid USB device when connected to the PROG mirco usb port. On linux i see for example: [85564.500749] usb 2-1.2: new high-speed USB device number 80 using ehci-pci [85579.582195] usb 2-1.2: device descriptor read/64, error -110 [85594.764710] usb 2-1.2: device descriptor read/64, error -110 I played now a little bit with it, and are pritty convinced that the content of the EEPROM for the FX2 is damaged. Sadly i cannot find a copy of the eeprom content for atlys on the internet. I actuallys found one from
  8. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that th
  9. Hi FPGA gurus ! I am facing trouble while trying to attach my Atlys USB JTAG device to a Centos 6 virtualbox VM. I recently had no choice but to upgrade my computer from Windows 7 to Windows 10. As a Windows 10 version of ISE 14.7 was available, I decided I could do the upgrade before realizing that ISE 14.7 for Windows 10 was indeed ISE 14.7 for Linux running a VirtualBox... Nevermind. The problem is that it seems I can't attach Digilent USB JTAG to the VirtualBox. Here is my configuration : Windows 10 Pro VirtualBox 5.2.8 (I upgraded it so that I could install Extensions
  10. Hi, Does anyone know if/where I can find an AXI4 example running on Atlys similar in functionnality to the HDMI PLB demo ? The example would show how to read frames from HDMI in, store to memory via AXI4 VDMA core, and read from memory to HDMI out. Thanx !
  11. Hi, In the atlys_rm_v2 doc page 14, it is mentioned " An EDK reference design available on the Digilent website (and included as a part of the User Demo) displays a gradient color bar on an HDMI-connected monitor", however I cannot find this project in the resource center, would you please give me this project ? Thanks in advance,
  12. I downloaded the demo project of configuring SPI flash and DDR2 memories controllers from this link, I would like to use the two controllers for my own application, the problem is the project is not associated with a documentation that explains the steps required for testing the peripherals of the system, can you please guide of how to test the two components mnetioned above ?
  13. Hi, I am trying to use the videotiming controller provided in the VmodCam demo project to display static images on an HDMI screen, my problem is that the size of images used is different from the rersolution selected by the controller, can I modify the code to add a new resolution ?
  14. Hi, Could you please explain how the read and write batches are used in the frame buffer controller ?
  15. Hi everyone, I've been reading Xilinx's DS643 pdf on MPMC configuration (v6.06.a). Table 91 page 170 lists the maximum frequency that can be used for the VFBC interface clocks, VFBC_Cmd_Clk, VFBC_Wd_Clk and VFBC_Rd_Clk. Only Spartan-3A DSP, Virtex-4 and Virtex-5 devices are listed. Where can I find the maximum frequency that can be used to clock VFBC on Atlys spartan-6 ? Thanx a lot, cheers.
  16. Hi FPGA gurus ! I'm trying to achieve video processing with Atlys board. My goal is to real-time rotate some VGA Stream ([email protected]) form hdmi input to 720p hdmi output. Rotation is 90° clockwise. The attached picture sketches what i'm aiming at. I've been thinking of using HDMI Demo project for this. I am a total noob to all this FPGA thing, i'm slowy trying to learn but it's not that simple when you don't know anything about electronics =) From what I have understood, in the HDMI demo the frame in written to DDR2 memory with a single call to the VFBC. TMDS data
  17. Hi I'm trying to transmit digital signals through a cable. In orther to avoid noise, I am using a differential output (LVDS) to transmit the information from the FPGA to a Cable. At the end of the cable, I'm using a converter to convert the differential signal to a single-end signal (LVDS to Single End converter). For that I need to feed my converter circuit through pin 6 of pmod connector (pin6 = vcc pin = 3.3V). Initially everything was working properly. However the other day, I switched on the board again (Atlys Board) and checked that I no longer have vcc on pin 6 (pin6 = vcc pin = 0V)
  18. Hi all FPGA fans and gurus ! First off : I am a total noob at all those FPGA and electronics things. So please be patient with me Now, for my problem : I recently got a second hand Atlys Board. My goal is to program it so that it can realtime rotate some hdmi input to its output. The input is a [email protected] signal. The goal is to rotate it and output a [email protected] signal (640 pixels fit in 720, with black borders 40 pixels wide each side). So, as I don't know anything about FPGA programming, I downloaded the following EDK HDMI demo on the Atlys resource page, I thought it wou
  19. Zygot goes back to the future to transfer data between two FPGA boards at 600 MB/s. Along the way he has a debugging adventure, learns ( AGAIN!!! ) why free stuff rarely is free and remembers when Digilent made FPGA boards that were great for development projects. This is a nice project for beginners or old hands to read through even if you don't have the hardware. CAUTION!!! You must read through the README text file before trying to replicate this project in hardware. Release 2 fixes some bad commentary in the source files and improves the behaviour of the UART transmit
  20. Hi, I recently purchased the pmodbt2 bluetooth interface module and tried interfacing it with the Atlys board. I used the GPIO demo bit file which was given in the forum for verification (after modifying it), but I was not able to see the output in the terminal software (Teraterm). I followed the instructions given in the demo, but I was not able to see the output; are there any specific changes I need to make in the module or in the terminal software? Can someone help me out with this? Ishan
  21. Hi, For a project, I want to align two input HDMI video sources in Atlys Spartan 6. I want to implement an asynchronous FIFO which will synchronize video source B with video source A timings (picture attached). However, the FIFO should be of the size to store atleast 8 MB (frame size of each video source = 1920*1080*32 bits). How to implement this asynchronous FIFO in Atlys Spartan 6? My atlys kit has MIRA P3R1GE4JGF DDR2 IC on it instead of Micron MT47H64M16xx-25E which is in older boards of Atlys Spartan 6. I am using ISE Design Suite 14.2 and running Xapp495. The frame rate that I am w
  22. Hi Jon, I am trying to use the ISE demo project that configures VmodCam video feeds at resolution 1600x900 using HDMI port, I made the following modifications: - Fist of all, I removed the framebuffer controller of DDR2 and replace by a BRAM controller. - I am trying to read one frame from camera A and sending it to pc through UART, I Implemented an RGB-to-grayscale converter in order to minimize the memory usage 3 times. Each time I store 1600 bytes in the BRAM and then sends them through the UART transmitting interface, however there is a big difference between the data transf
  23. I want to build an Audio Processor using Diligent Atlys. I want to know whether is it practically realizable??? I don't have dedicated faculty in my college due to which i will require help . Has anyone done it in the past so that he or she could help me or guide me if i could get stuck???