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Found 3 results

  1. Hello , I am using VIVADO 2018.2 HLx editions (Windows) Do you have the steps required program the Digilent ARTY Z7 -20 SPI flash with a standalone FPGA design? I have followed a number of web examples that claim to show the route to follow none of which work. They are either incomplete or for the wrong version of ARTY , VIVADO and SDK. Thanks
  2. Dear All, Me and a colleague of mine are facing an SPI timeout issue on a Zynq. We already posted the issue in the Xilinx forum: https://forums.xilinx.com/t5/Embedded-Linux/SPI-transfer-timeout/td-p/833550 but we did not receive any answer, yet. So I would like to ask your help. I am trying to use a TFT LCD screen with the Digilent Artyz7, exploiting the frame buffer. I created a project on Vivado that exports the Zynq PS SPI interface through EMIO. I have already deployed the linux-digilent kernel (v4.4.0) on the Zynq and I am able to see the SPI peripheral under /sys/class/spi_master/spi2.0 (the device tree has been generated using SDK). Thus, as soon as I try to insert the kernel module for the frame buffer support, I get the following error: spi2.0: SPI transfer timed out I attach the images from the logic analyzer: The kernel module of the frame buffer sends the data correctly through the SPI interface before going to timeout state. Any ideas or suggestions regarding this issue? Thanks a lot. Best Regards, Enrico
  3. Hi all, I started playing around with an Arty Z7 board and downloaded the hdmi out demo. As a first test, I used the bitfile from the SDK and loaded into the FPGA with the Xilinx SDK 2017.3. I guess with the provided bitfile, SDK version does not matter... JTAG jumper set. FPGA configured successfully I used the SDK terminal to connect to serial port but still do not get any output like depicted in https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start Also I do not get any signal on my display through HDMI cable. What am I doing wrong? Thank you very much in advance!