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Showing results for tags 'artyz7-20'.
Hello, I hope you will be enjoying your vacations if you have been given some. For me this has meant finally being able to work on my spare-time experiment and finally reach closure on my upgraded design. Let me describe the process. The ArtyZ7-20 is just the initial prototyping. I'm going to move to real production FPGA boards ASAP (probably in August) but for the time being I'd just want to go ahead with the Arty. The system is systemverilog RTL and barebone C++. The initial design was 100Mhz and 6-stage pipe. Vivado estimated about 2.2W power. I suspect it was much lo
I've given up on working with the Arty Z7-20 with 20.1 and reverted to Vivado 19.1 and the 19.1 SoCSDK. Using petalinux tools and Petalinux-Arty-Z7-20 project I've been able to create a bootable Linux SD image. So far so good! My objective is to port a project adding AXI slave IP, Linux drivers and applications. The aforementioned project contains a Petalinux-Arty-Z7-20-2017.4-1.bsp file which in turn contains the projects matching Arty_Z7_20_wrapper.bit IP. This project seems like a good starting point for what I need, but where can I find the correct project used to generate Arty_Z7_20_wr
I've got an Arty Z7-20 board. It's powered by an external wall-wart (USB power isn't enough). I cloned the git repo from here: https://github.com/Digilent/Petalinux-Arty-Z7-20 Then I copied the BOOT.bin and images.ub files from Arty-Z7-20/pre-built/linux/images/ onto a microSD card. Plugged the microSD card into the Arty slot, powered on the board. PuTTY is connected on COM10, I see the boot spew and get to a prompt. Login as root/root. I see that the dropbear SSH server is started, so I scp my .bit file over. Then I want to reconfigure the PL with my own bit file