Search the Community

Showing results for tags 'arty7'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 5 results

  1. Hi, I am having a problem with GPIO interrtupt on Arty A7 board. + 2 GPIO with each of them is dual channel. + INTC instance to connect the interrtup with Microblaze. After I used below software, I can not see the interrupt. Would you please tell me how to debug in next step ? Sorry, I am new to SDK and Arty A7. I want to connect the switch or button as interrupt, and do some task inside a handler. I want to clarify below of my understanding, whether it is correct or not: 1. hardware: - Enable register access in INTC to make the software can access INTC registers. - Choose level (high) as interrupt type. - Fast interrupt is enable. 2. Software: #--------------------------------- /***************************** Include Files *********************************/ #include "xparameters.h" #include "xil_exception.h" #include "xintc.h" #include "xgpio.h" #include "xil_printf.h" #define UART_INT_CHANNEL 0 #define GPIO0_INT_CHANNEL 1 #define GPIO1_INT_CHANNEL 2 XGpio Gpio0; /* The Instance of the GPIO0 Driver */ XGpio Gpio1; /* The Instance of the GPIO1 Driver */ XIntc Intc; /* The Instance of the Interrupt Controller Driver */ void UART_HANDLER(void *Callbackref); void GPIO0_HANDLER(void *Callbackref); void GPIO1_HANDLER(void *Callbackref); void GPIO0_HANDLER(void *Callbackref) { xil_printf("Handler GPIO0 !! \r\n"); //write out GPIO0, LED 0101 XGpio_DiscreteWrite(&Gpio0, 1, 0x05); //Write out GPIO1, LED RGB XGpio_DiscreteWrite(&Gpio1, 1, 0xAA55); } // Main program int main(void) { // 0. Initial GPIO0 Status = XGpio_Initialize(&Gpio1, XPAR_GPIO_1_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } //Configure the IO direction for GPIO0 ( push button is in channel2): XGpio_SetDataDirection(&Gpio1, 1, 0x00000 ); XGpio_SetDataDirection(&Gpio1, 2, 0xFFFFF ); //1. Init the Interrupt controller Status = XIntc_Initialize(&Intc, 0); if (Status != XST_SUCCESS) { return XST_FAILURE; } //2. Connect the handlers Status = XIntc_Connect(&Intc, GPIO0_INT_CHANNEL, (XInterruptHandler) &GPIO0_HANDLER, (void *) 0); if (Status != XST_SUCCESS) { return XST_FAILURE; } //3. Enable the INTC XIntc_Enable(&Intc, GPIO0_INT_CHANNEL); XIntc_Enable(&Intc, GPIO1_INT_CHANNEL); //4. Start the INTC Status = XIntc_Start(&Intc, XIN_REAL_MODE); if (Status != XST_SUCCESS) { return XST_FAILURE; } //5. Enable interrupt for GPIO0 XGpio_InterruptEnable( &Gpio0, 0x0000); XGpio_InterruptGlobalEnable( &Gpio0 ); // 6. Initi the exception Xil_ExceptionInit(); // Xil_ExceptionRegisterHandler(1, (Xil_ExceptionHandler)GPIO0_HANDLER, 0); // // /* Enable non-critical exceptions */ Xil_ExceptionEnable(); xil_printf("Waiting for interrupt... !! \r\n"); while(1) { } //return return XST_SUCCESS; } //--------------------------------------------------------------------------------
  2. Hello, I'm trying to build this demo: https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start and I have error while generating project (after run in console "source ./create_project.tcl") WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' Please help Any idea why it happens? I have: Windows 8.1 Vivado 2016.4 HLx WebPACK
  3. I'm trying to run the HDMI-in and HDMI-out demos on my ARTY Z7 board and I'm having problems building the SDK side of the projects. The problems are the same for both of these projects. After importing the project in the SDK I get the following error: 09:07:45 ERROR : The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace. As a result, this BSP will not build properly. To fix this error, please import the associated hardware project or recreate a new BSP targeting an existing hardware platform. Upon building the project I get the following errors (sorry for the Polish): Description Resource Path Location Type ../config.make: No such file or directory hdmi_in_bsp line 38 C/C++ Problem config.make: No such file or directory hdmi_in_bsp line 33 C/C++ Problem fatal error: xil_types.h: No such file or directory video_capture.h /hdmi_in/src/video_capture line 74 C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/axivdma_v6_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/coresightps_dcc_v1_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/ddrps_v1_0/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/devcfg_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/dmaps_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/emacps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpio_v4_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpiops_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/iicps_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/qspips_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scugic_v3_5/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scutimer_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/sdps_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/standalone_v6_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/uartps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/usbps_v2_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/vtc_v7_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/xadcps_v2_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [src/video_capture/video_capture.o] Błąd 1 hdmi_in C/C++ Problem make[1]: *** [coresightps_dcc_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [profile_includes] Błąd 2 hdmi_in_bsp C/C++ Problem make[1]: *** [scugic_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scutimer_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scuwdt_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [standalone_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xadcps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xddrps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdevcfg_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdmaps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xemacps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xgpiops_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xiicps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xqspips_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xsdps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xuartps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xusbps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** Brak reguł do wykonania obiektu `config.make'. hdmi_in_bsp C/C++ Problem make[2]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[2]: *** Brak reguł do wykonania obiektu `../config.make'. hdmi_in_bsp C/C++ Problem While building the project in Vivado I had some other problems which I manged to solve. I described my build below. I have followed the instructions on Digilent's reference site for the project, that is: I'm using Vivado 2016.4, I've installed the board suport files, I've cloned the demos from the Digilent github repo along with the Vivado library IP-cores I've successfully generated the projects via the tcl script with one warning, which doesn't look critical: WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_0/aRst_n(rst) Next I ran the Generate Bitstream option and got an error that the top module wasn't set. I've set the top module to hdmi_out and went through elaboration and synthesis where I got the following warnings: [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":82] [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":83] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":5] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/hdmi_in_v_vid_in_axi4s_0_0_clocks.xdc":11] [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Pfi 67-13] Hardware Handoff file hdmi_in_processing_system7_0_0.hwdef does not exist for instance processing_system7_0/inst Finally on bitstream generation I got the following error: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 6 out of 153 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DDC_scl_i, DDC_scl_o, DDC_scl_t, DDC_sda_i, DDC_sda_o, DDC_sda_t. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. I've used the fix from https://www.xilinx.com/support/answers/56354.html to ignore these rules and managed to get a bitstream. Next, following the tutorial, I've exported the hardware along with the bitstream, but the export failed because no Hardware Handoff file was found. I followed the suggestions from https://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Export-Hardware-Hardware-handoff-file-sysdef-does-not/td-p/539953 to manually generate the .sysdef file, and I managed to export the hardware and open the design in the SDK. I'm suspecting that the problem might be caused by the fact that I'm using Vivado installed by a different Windows user. I tried adding the Vivado and SDK location to the path variable, setting xilinx_sdk and xilinx_vivado variables, running the settings_64.bat scripts etc. but that didn't improve the outputs.
  4. Hi All, I have been working through the Arty - Getting Started with Microblaze project in the resource folder with the Artix-7 FPGA Development Board. When I get to step 11.2 Program the FPGA I get the following message Program FPGA failed Reason: Could not find FPGA device on the board for connection 'Local'. I have been stuck here for the last couple week and have tried several times to track down the connection issue. So far no luck. Any assistance would be greatly appreciated. Thanks, Don
  5. am using the ARTY 7 evaluation board from digilent which used the Artix-7 x35AT cpg324 packaging. Using one of the general purpose I/O banks i want to configure it for 1.8V configuration. (I am using this for 3-wire SPI to generate the spi clock and read the output from my ADC which are at 1.8V) I looked through the documentation to configure this on the board and after going through all the relevant documents i am still unable to configure the I/O to LVCMOS18 standard. Here is the table which mentions how to configure the files And here is how i have configured in the XDC file set_property IOSTANDARD LVCMOS18 [get_ports adc_conv_oc] set_property IOSTANDARD LVCMOS18 [get_ports adc_din] set_property IOSTANDARD LVCMOS18 [get_ports adc_sclk] set_property PACKAGE_PIN V15 [get_ports adc_conv_oc] set_property PACKAGE_PIN U16 [get_ports adc_din] set_property PACKAGE_PIN T11 [get_ports adc_sclk] set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CFGBVS GND [current_design] The synthesized design has the following I/O port which indicates that the I?O's are configured for LVCMOS18 on bank 14 and VCC = 1.8V The UG470 documentation mentions the following: The 7 series FPGAs have two I/O bank types: high-range (HR I/O) banks support 3.3V,2.5V, and a few lower voltage I/O standards, and high-performance (HP I/O) banks support I/O standards of 1.8V or lower voltage. The dedicated configuration and JTAG I/O are located in bank 0. Bank 0 is a high-range bank type on all devices except for the Virtex-7 HT devices. Several of the configuration modes also rely on pins in bank 14 and/or bank 15. Bank 14 and bank 15 are HR I/O banks in the Spartan-7, Artix-7 and Kintex-7 families, but are always HP I/O banks in the Virtex-7 family. See UG475, 7 seriesFPGAs Packaging and Pinout Guide for bank information for each device. Note: The CFGBVS pin is not available on Virtex-7 HT devices. Virtex-7 HT devices support only 1.8V operation for configuration banks. The CFGBVS pin setting determines the I/O voltage support for bank 0 at all times, and for bank 14 and bank 15 during configuration. The VCCO supply for each configuration bankmust match the CFGBVS selection if used during configuration — 2.5V or 3.3V if CFGBVS is tied to VCCO_0, and 1.8V or 1.5V if CFGBVS is tied to GND. but somehow i always get the output to be 3.3V. Any ideas on how to solve this? Does the Arty-7 evaluation board for some reason not allow me to configure the voltages to LVCMOS18? Thanks