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Found 170 results

  1. Hi, I have done a project for ARTY board which uses a bootloader to run my software application following this tutorial: How To Store Your SDK Project in SPI Flash My problem is that it works only after I press the PROG botton. So, after I connect the power, the FPGA PL get programmed (I see LED blinking correctly), but it seems that the bootloader does not. Only after I press PROG it does. What should I do to avoid pressing PROG at the beginning? Thanks, Lorenzo
  2. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  3. i wanted to interface multiple digital serialiser with arty A7 35T board through pmod pins. And transmit the same data through UART. help me with the verilog code and other resource.
  4. Hi, First I tried with Nexys K7, here another try with Arty K7. There is now a great portfolio of Arty boards, spanning Spartan-7, Artix-7 and Zynq. The only thing missing is an Arty with a Kintex-7. And is seems imho well in reach, the XC7K70T is with ~$120 only $10 more expensive then the XC7A100T used on the Arty A7-100. So a Arty K7-70 should be possible at a reasonable price, slightly above the Arty A7-100. With that offer the Arty family would cover Arty S7 -- Spartan-7 and lowest cost Arty A7 -- Artix-7 Arty K7 -- Kintex-7 and highest speed Arty Z7 -- Zynq and embedded processor Maybe somebody from Digilent can comment on this. Or users who'd like to buy such a board  With best regards, Walter
  5. Could I get voucher license having ARTY A7 board without one in the kit? I bought the new ARTY A7 but it doesn't have voucher license in the box. Thanks in advance)
  6. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY. A few questions come to mind: Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors... Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.
  7. Hi all, I'm having trouble getting a spi module set to 'slave mode' to read data. I'm working with the Arty Board and attached is my Vivado block diagram. The SPI module that I'm having trouble with is 'axi_quad_spi_0'. I've set the IP to be in standard and unchecked Master Mode in the SPI Options. I set the FIFO to 256 and Freq Ratio 16x30. I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing. The other registers of axi_quad_spi_0 read as follows: Reg 0x60 => 0x18a Reg 0x64 => 0x25 Reg 0x70 => 0x01 whether or not the master device is sending SPI. The output from these registers seem sort of reasonable, but I would hope the flag in reg 0x64 bit 5 to go to 0 in the case axi_quad_spi_0 clks spi data in, but it isn't, which is consistent with readreg 0x6C returning 0x00. I also tried connecting outputs of a master spi module to another slave spi module 'axi_quad_spi_2' and got the same result (see block diagram). I've also tried, the xilinx spi polled mode examples and can't seem to get those working either. See below for some relevant SDK code. Can someone tell me what I might be doing wrong? Is there something more fundamental that I don't understand? Thanks! Best, Mike http://tinypic.com/view.php?pic=2vmbjg6&s=9#.WNLezbIrJaQ #define spi_dev_id2 XPAR_SPI_2_BASEADDR void simple_receive() { int data; XSpi_WriteReg(spi_dev_id2,0x60,0x1EA); XSpi_WriteReg(spi_dev_id2,0x70,0x1); XSpi_WriteReg(spi_dev_id2,0x28,0x80); data = XSpi_ReadReg(spi_dev_id2,0x6C); printf("Lithe Buffer Simple %#02x\r\n",data); }
  8. I went through the process of running MIG7 (Vivado 18.3) to generate a DDR3 controller for the Arty A7-100. I copied the digilent board files into the Vivado 18.3 board_files directory and chose arty-a7-100 when opening my project. When MIG7 starts, the first thing it wants is clock period. That's where I'm having the problem. MIG7 allows numbers between 2500 and 3300ps. But with my board, MIG7 won't allow any period less than 3225ps. That's a very narrow range of frequencies! I need to consider my FPGA general system clock speed in connection with making a high-speed UART for PC communication. Between 3225ps (310.7Mhz) and 3300ps (303Mhz), there are no useful frequencies I can find in common with baud rates that are multiples of 1,000,000. If the tool allowed 3333ps, I'd end up with an FPGA clock of 150Mhz (with 2:1 ratio). I could make that work easily. After looking at the "stub" Verilog file and reading in UG586, I see that sys_clk_i is a user input. Could I not feed 300Mhz in there? I don't care that memory would be a tiny amount slower. Would the DDR controller not work? Is there any reason the tool could not directly allow a slower clock specification? Thanks for all your help. Let me know if any file I have would be helpful to you on this. Allan
  9. I am running Vivado 18.3 on Ubuntu 18.04, and cannot connect to my Arty board. While troubleshooting, I found directions on installing cable drivers and board files (https://reference.digilentinc.com/vivado/installing-vivado/start), however I cannot find the path referenced in 2.1. I have an /opt directory, but it is empty, and while I can find a couple /data directories that look like they could be correct, none of them contain a xicom (or .xicom) directory. Note: I installed Vivado a while back but never got around to playing with the board until now. I wanted to exhaust all options before trying a fresh install of Vivado. SOLUTION UPDATE: I found the correct directory path by typing "which vivado" into the terminal, which pointed me to /tools/Xilinx/Vivado instead of /opt/Xilinx/Vivado
  10. I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this: and looking at this diagram: Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output. But here is the usb_uart interface spec in the ./board_files/arty-a7-35/E.0/board.xml file : <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset"> <preferred_ips> <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/> </preferred_ips> <port_maps> <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out"> <!--Change to “in”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_txd"/> </pin_maps> </port_map> <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in"> <!--Change to “out”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_rxd"/> </pin_maps> </port_map> </port_maps> </interface> So, usb_uart_txd should be "in", usb_uart_rxd should be "out". When I change this, the UartLite serial port works! I tried to change the direction of the pins in the Project HDL "wrapper" to no avail. Please note that this default config is found in the board.xml files for arty, arty-A7 and arty-S7. Do the board.xml files need to be changed? Is there some other way to change pin direction in the Vivado Project?
  11. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for correct identification) to replace the resistors manually with a lower value? Thank you for your time!
  12. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  13. Hello, I am wondering what is the best way to share a big chunk of memory between two cores of Arty-Z7-10? Note that I have already gone through the XAPP1079 of Xilinx, however this tutorial does not really share the DDR memory between two cores. It only uses OCM to share a semaphore between two cores, so two cores can share the terminal. To give you more detail on what my goal is: I want to read a big chunk of data (something in oder of 15 - 30 MB) on CPU#0 and put that into DDR memory, and then let the CPU#1 know when I am done via a flag (which I know how to do with OCM). Following this, I want CPU#1 to access the data that CPU#0 put in DDR and write it to the SD card, while CPU#0 starts to read the 2nd chunk of data. To do this, it is clear that I need to modify the ldscript of two cores, so they share part of the memory. I wonder if anyone has done such kind of thing before and have any suggestion? Regards, Mahdi
  14. Hello, I am trying to develop a simple verilog code on Arty-Z7-10 that writes to the SD card on the PL side, without having to use SDK software. To do so, I believe I need to setup my SD card pins as EMIO in the ZYNQ and modify the constraint file to uses correct pin mapping. However, I wonder if anyone has done such type of coding before and is able to provide me with more detailed information. I found this tutorial which has tried to do same thing with SPI, but it was not very detailed. https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part193-The-Zynq-SoC-s-EMIO/ba-p/764971 I also found such SD card controller for Nexys4 board, while it seems a bit challenging to get it to work with Arty Z7 board due to different pin mappings. https://web.mit.edu/6.111/www/f2015/tools/sd_controller.v Any help is appreciated. Thanks, Mahdi
  15. Hello, I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue. Best, Mahdi
  16. We have purchased a ARTY A7 board, as well we are using VIVADO 2018.3 (IDE). We downloaded the board supported files from below link as under " (3.1) Installing Digilent Board Files". https://reference.digilentinc.com/vivado/installing-vivado/start In the downloaded files we get .prj file and XML format files , while using vivado 2018.3 tool, it accepts only .xpr, .ppr, .xise formats. Please suggest me how to use board supported files in vivado 2018.3.
  17. We have purchased a ARTY A7 board, as well we are using VIVADO 2018.3 (IDE). We downloaded the board supported files from below link as under " (3.1) Installing Digilent Board Files". https://reference.digilentinc.com/vivado/installing-vivado/start In the downloaded files we get .prj file and XML format files , while using vivado 2018.3 tool, it accepts only .xpr, .ppr, .xise formats. Please suggest me how to use board supported files in vivado 2018.3.
  18. Hello everybody, I'm new to this forum and to fpga programing and I got a question: is it possible to implement a linux on microblaze and having non linux-managed blocks (classic logical blocks) at the same time? and how to realize that. I got the webpack suite of Xilinx (vivado + sdk), i'm working on windows but got a ubuntu virtual machine ready. To define the project, a little draw: For the linux implementation, i found @loberman manual, i was close by myself but it's realy helpfull. Thanks guys
  19. Hello, What is the status with the the FreeRTOS running on a FULL implementation of a Microblaze on ARTY ? I bought this board for this specific purpose following your presentation video : https://www.youtube.com/watch?v=NF7ryZH8lxE Regards
  20. John1123

    ARTY FPGA

    Hi, I don't really know where to post this but I have a question. I am very new to FPGAs so this may seem as a very stupid question. i wanted to use my ARTY and read values from the analog IO and output the values through UART. I am familiar with setting up UART and microblaze but I have no idea how to use the analog IO. Any help will be kindly appreciated.
  21. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx
  22. Hello all, some months ago I had a Basys 2 Board that I perfectly could program via multisim, designing an schematic and then exporting the design. Now I have an Arty S7 on my hands and I would wish to do the same. I followed the tutorials: http://www.ni.com/tutorial/14871/en/ and https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start An instance for the Arty S7 was created in multisim and it gave me the option to generate the VHDL file from the design (I haven't verified the file yet). Multisim won't give me the programming option. I checked the configuration files for others working boards and there is a missing line for programming, like Device ID etc. Mi question, does anybody has tested programming the arty s7 from multisim? if not is it possible? directions ? Best Regards, Edwin Marte
  23. Hello, I am working on a dual core project with mailbox IP on a Arty Z7-10 board which has been acting inconsistently. In my project, 1st core is receiving data from FPGA and sending it through mailbox to the 2nd core; the 2nd core is supposed to receive and write them to the SD card. I need to write the data at 0.5 to 1 MB/s speed, so I can not read and write fast enough on one core. As an example to show the problem, I am writing a number to the card that is being incremented by one on a loop, and plot that versus the clock cycles. Supposedly, my output should look like a straight line which it does if I do all of this on one core. Now, If I use the mailbox to send the same value between two cores, and write it on the 2nd core, I am seeing gaps and overlaps in my data which I am pretty sure is because of Mailbox. Here are two examples of what is happening. If you zoom into the time = 1.0, you can see the following gaps, and overlaps. I have set the size of mailbox at 2048, and made sure that it never fills up by checking its status on every loop. So I wonder what could be the reason for these gaps and overlaps? Can't Mailbox IP transfer data consistently between two cores? Is there any other method for doing such jobs? Thanks, Mahdi
  24. Hello! I'm using an Arty-S7 with a PMODOLED. I want to draw several rectangles on the little display, but the example design seems to delete the previous rectangle when I add a new one. Is there some magic to display multiple rectangles or do I need to dig deeper and hack on OledGrph.c? Thanks! Craig
  25. Hi There, I'm using an Arty-S7 board and am connecting PMODOLEDs to all 4 PMOD connecters (JA, JB, JC, JD). The example that comes with the driver only talks to the PMOD connected to JA, and it works like a champ. Looking at the code and header files, though, I'm not seeing how to talk to the other PMODs. What should I change to talk to the PMODOLEDs on JB, JC or JD. Be gentle, I'm really a hardware guy and using this to learn a little more about C-programming and to that end, the less amount of hacking needed the better. Thanks! Craig