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Found 131 results

  1. Hello! We have purchased a number of the Arty boards for some testing we are doing, and would like to be able to clear or reset any/all memory on board to the original state. -- Can Digilent provide a Statement of Volatility for the Arty Z7 and A7 (and original Arty if different from the A7)? -- For any non-volatile memory on these Arty boards, can Digilent provide a procedure to return the memory to the "fresh from Digilent" state? Thanks in advance! Jeff
  2. How to use DDR3 on Xilinx Arty board?

    I have been trying to use the MIG in Vivado to work with the Xilinx Arty on-board DDR3 chip. So far I have gotten nothing but errors and dead ends from tutorials and documentation. Does anyone know of the best and simplest way to communicate with the RAM?
  3. Vivado not finding Arty target

    I've installed Vivado v2017.4 on a CentOS 7.4 system. The ARTY board JTAG/UART is connected to a USB port on the host system. When I start Vivado, and start the Hardware Manager, it shows that there is a server running on "localhost" but does not list any target boards. Clicking on "Auto Connect" does nothing. The Hardware Server Properties window says that Vivado is connected to the server. Running "lsusb" on the host shows two ftdi_sio USB Serial Devices which are attached to /dev/ttyUSB0 and /dev/ttyUSB1. Any suggestions?
  4. Axi DMA timing

    Hi all, i am using the DMA to send data from my DDS-compiler to DDR on the Arty board. The data transfer works in general, but actual the timing is wrong. My actual Design: I generate a 2 Hz clock and transfer with 2 Hz values from the DDS to the DMA. The problem is, if i start the simple_poll-function from this code/design (http://i.imgur.com/7v0d7NF.png) it takes the same value many times. So finally the aim is to get a value every time the DDS provides a new one. Thanks to everyone who can help!
  5. arty xc7S50 vivado support win 8.1

    which version of the vivado do I need for win 8.1 xc7S50 arty board thanks in advance DC note 2014.4 doesn't have the chip listed note 2017.4 says its for windows on the install page but then later says it don't support 8.1 and also crashes on 8.1
  6. Comparison between Pynq and Arty

    Hello, I was wondering what the differences between Pynq and Arty are. I also was wondering if I could use a Pynq just as an Arty, since Pynq is much inexpensive than Arty with the academic pricing. Thanks
  7. Hello Digilent, I am just going to buy an ARTY A7 35T board and I have to interface an external ADC ADC7091R with it. I know it has an on board XADC but I need to do for some specific purpose. Now I have seen a Pmod of ADC7091 R given in its datasheet and I want to know that "DO ARTY A7 support pmod of ADC7091R". Thanks
  8. DDR3 Usage

    Hello there, for six month I am learning VHDL, FPGA and related with an Artix-7 FPGA Development Board [1]. Now I am trying to access the onboard DDR3 memory for reading and writing. For convenience I try to avoid writing my onw DDR3 Interface, so I was looking at several IP cores. My plan was configuring a suitable IP core and create an HDL Wrapper, so that I can access it from my VHDL code. I tried the Memory Interface Generator, but on the other end it has an AXI Slave Interface. So it seems that one interface I have to implement by myself. Is there any simple solution or way, how to use DDR3 Memory? Something like Block Memory Generator provides. This interface is simple, which is easy to use for a beginne like me. blueshark [1] https://reference.digilentinc.com/reference/programmable-logic/arty/start
  9. Hello. I have developed a Microblaze project based on a Digilent Vivado 2016.4 project for the Arty board that I downloaded a year ago. (microblaze server I believe). Everything works in Vivado 2016.4, I can go through the entire implementation to bitstream and SDK export. When upgrading to Vivado 2017.4, I get these errors referring to some encrypted files. In reference to error [Synth 8-5809] I have found this not-to-helpful answer record, referring to FLIT width in an XHMC IP that I dont think is eve nin the project, with no information on how to change it. https://www.xilinx.com/support/answers/68421.html Regarding the second error [synth 8-285] I found this, which claims the problem was in 2016.2, but still appears, so I am skeptical of this solution. Was the default changed back to OOC per IP with 2017.4? I am not sure what generate_target means or does, or when it is processed in the GUI workflow. So I am not sure when to do this in the workflow or what it will do. https://www.xilinx.com/support/answers/68238.html In Vivado 2016.3 there was a change to the default BD generation mode. The default was changed from Global to Out of Context (OOC) per IP. You will not typically see this problem when migrating an existing project because the migration script will maintain the existing generation mode setting. However, in a scripted flow where the entire project or design is being recreated, the new default settings would apply unless explicitly changed. Additionally, the "OOC per IP" BD generation is not allowed in non-project mode. Therefore, starting in Vivado 2016.3, if you are using a scripted non-project mode, you will need to set the BD generation back to global. To do this, set the synth_checkpoint_mode to None (Global synthesis) before generating targets. For example: set_property synth_checkpoint_mode None [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] generate_target all [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] Can someone assist me in this upgrade? I imagine Digilent will be upgrading their example projects at some point. Now would be a great time! Thank you!
  10. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to 4 LEDs on the board. The purpose is to monitor the high nibble of a 32-bit ALU calculation using the LEDs on the Arty board. The design works under behavioral simulation, and it elaborates correctly (see attached schematic of the elaborated design). However, when I synthesize the design, it is reduced to almost nothing -- with the clock and reset pins routed nowhere, and the LED pins routed to some buffers connected to ground. The entire internals of the design are removed (see included schematic of the synthesized design). Can anyone help me figure out why this is happening? Here are the sources of the upper levels of the design, and the relevant constraints that I've applied for the FPGA board: SOURCES: ---------------- -- pindelivery.vhd -- Routes package pins to logical units library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity pindelivery is Port ( clk_in : in STD_LOGIC; rst_in : in STD_LOGIC; leds_out : out STD_LOGIC_VECTOR (3 downto 0)); end pindelivery; architecture behavioral of pindelivery is component topLevel_debug port (clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector(3 downto 0)); end component; signal rst_out : std_logic := '0'; begin rst_out <= not rst_in; tld1 : topLevel_debug port map (clk => clk_in, rst => rst_out, led_out => leds_out); end behavioral; ---------------- -- topLevel_debug.vhd -- Top-level module for debug library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity topLevel_debug is port ( clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector (3 downto 0)); end topLevel_debug; architecture behavioral of topLevel_debug is component controlTest port (clk : in std_logic; rst : in std_logic; r0_highnibble : out std_logic_vector(3 downto 0)); end component; begin cpu1 : controlTest port map (clk => clk, rst => rst, r0_highnibble => led_out); end behavioral; ---------------- CONSTRAINTS: ---------------- ## Clock signal set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { clk_in }]; ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { leds_out[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { leds_out[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Reset button set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { rst_in }]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property INTERNAL_VREF 0.675 [get_iobanks 34] ---------------- Any assistance would be much appreciated! Thanks, Curt Pehrson
  11. Transform pins into Pmods

    Here are 22+34=56 pins and I must add 4 pmods. How to declare in the IP INTEGRATOR pairs of pins as a Pmod entry?
  12. AXI DMA and Microblaze

    Hello All, I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples. I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the transfer length to be. But if I do another transfer, and all subsequent transfers from then on, they seem to be equal to the length which was programmed. I initially thought that this was a caching issue (and still may be), but I've since disabled caching in the software. I've also provided an image below of my Microblaze, and to my understanding there is no caching enabled (i've disabled cache when configuring the Microblaze in vivado). The type of DMA transfer that I am using is just a register direct transfer, not scatter gather. The M_AXI_DP is connected to an AXI Interconnect, of which the M_AXI port of the interconnect is connected to the S_AXI_LITE port of the DMA. Another interesting thing I've noticed is that, if I do an acquisition of ADC samples, read the DDR starting at address 0, and perform another read of DDR starting at address 0, it looks like the data at address 0 updates, but the following data is the same as the first read. P.S. I am still new to Digital Design, sorry if I've omitted any crucial information.
  13. Best software to program an Arty board

    What is the best software to program in C++/C an Arty board? I tried Vivado HLS but it is good only for algorithms not for the components of the board. The SDx made by Xilinx is not compatible with the boards. If are others programs can someone please provide tutorials/books for some examples in C.On Xilinx forum I couldn't find any tutorial for working with the board components in C.
  14. Hi, I've a requirement to interface a CMOS Image sensor(MT9P006) with Artix7 FPGA. I've to perform image processing including autofocus and interfacing with USB 3.0 peripheral controller IC. Is it possible with artix7??? If yes, then what are the tools (like vivado ISE etc) required and what will be the expected cost for those tools... Is there any free software alternatives for them??? Thank you...
  15. tl;dr: custom design for MIPI bridge to an Arty with no transceivers, besides coming to my senses, what's the best way to tackle this? --------------------------------------------- Summer uni project. My task is getting image data from a MIPI camera sensor (OV5467; the Raspberry Pi camera) into an Arty board. No high speed transceiver pins on it, and no native support for interfacing to MIPI. Just the HP IOs on the middle Pmods. Our fall-back is to just take image data in via the Raspberry Pi and squirt that via UART or SPI into the Arty to demonstrate parallelized image processing. However, the disparity between input-output rates and the rate at which our configured logic can process the image is so significant, we feel it's a waste of an FPGA. I have perused XAPP894, IOSelect resources for Artix-7 devices, and the IP catalogs in Vivado for CSI-2 Rx/Tx IP, etc. I think we can get the IP on a uni license. A faculty member helping us is keen to fabricate a custom PCB for bridging MIPI to other standards (like the LVDS_25 on the Arty). If I can bring him a viable design for this bridge he will get it fabricated. I think he might even take care of the PCB design as long as I can bring him a circuit schematic that will work. --------------------------------------------- My questions to y'all 1) should I go with a passive RC network (p10 of XAPP894) for D-PHY compliance or use a vendor-bought bridging IC? 1a) if an RC network, then how precise/accurate/tolerant do my passive component values need to be? 2) should I be simulating this bridge for signal integrity, say with Ibis in Altium, before submitting the design? (I have zero exposure to Altium, let alone simulating for signal integrity) 3) should we just consider switching to a Zedboard (there are a few floating around upstairs) if it has MIPI D-PHY compliant ports? Or is the challenge of a custom bridge worth it? (I am a virgin with this stuff, very little experience) --------------------------------------------- any other advice, comments, recommendations, jibes or anecdotes are more than welcome Thank you.
  16. Camera Sensor for Arty Z7-20?

    Hello, I am working on a project using an Z7-20 FPGA for computer vision processing using a CMOS camera sensor. I am planning to run convolutions on the image data for usage such as a Sobel filter. (to avoid RAM requirements, I will most likely use a Line Buffer to store the data while it is in use. This means I will need a camera sensor which can connect directly to the FPGA and outputs one pixel at a time (through multiple wires for each color), with a well-defined (or customizable) clock to synchronize the data transmission. I want like something cheap, rugged, and easy to wire like the OV7670 (as this is for a robot, I cannot use something too sensitive to vibration), but something that has a little higher resolution and framerate (I was thinking 480p or 720p at 60fps, or 1080p at 30fps, but lower is fine if the price is too expensive), as well as being a breakout board which can be easily wired (I can make a custom pin header adapter from the camera module to the FPGA's ports if needed, but I don't want to have to use a very small/thin one or something that requires SMD soldering). Any suggestions? Thanks in advance.
  17. Dear all, i am really new in working with FPGA's and started with some microblaze application. So i build up a standard microblaze system with uartlite and some LED's. Also i generate a sine wave with the dds-compiler and now i want control the input clock of the dds-compiler for changing the output frequency. For this i started to use the axi-Timer (i don't know this is the best way for an adjustable clock) and started to write a C programm in the Vivado SDK software. Till now i don't get any output from the axi-Timer, maybe someone can help me... Thank you! Following the C-code with already working LED's and uart communication:
  18. Arty-Z7-20 board

    Hello, i have since a few days a new arty-z-20 board and i like to learn from the rare examples for that board. I found one example which seems to be the base for Linux (Arty-Z7-20-linux_bd-master). This example was made with the Vivado 2016.4 Suite, but i use the current Vivado Suite (2017.3). In that example are two ip`s that could not be upgraded, because they no longer exists in the current Vivado Suite. Where can i get some working examples with Vivado 2017.3 and higher Support for my new Arty-Z7-20 board? My first Arty board was the Artix-7 "original" board. I had found all the examples that i needed to learn from the beginning to the full scale microblaze architecture. I made good experiences, but now i'am not happy with that arty-Z7-20 board! How do i build the simplest Zynq architecture with UART and "bare metal" OS? How do i build the very easiest Linux architecture and what ip's do i need for that? I have a lot more questions... Thank you...
  19. Hello, I bought Arty-A7 development board and I will use it for Risc5. How can I connect a host pc to this board for using openocd? This board has 'FT2232HQ' and does it mean that I can use USB port for JTAG and UART at the same time? (Or should I buy any other cables for using openocd?) Thanks,
  20. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  21. [Arty] signal order of J8 port

    Hello, everyone. We are planning to access JTAG by attaching a pin header to J8 of Arty board in order to confirm efuse access. (I dont use USB-JTAG.) Which signal corresponds to each of the six through holes of J8? I check the reference manual and circuit diagram, but there is no clear description. From the relationship with the D1 diode on the circuit diagram, I guess the following order. Is it correct? 1. TMS_JTAG (suquare, 1 pin mark?) 2. TDI_JTAG (circle) 3. TDO_JTAG (circle) 4.TCK_JTAG (circle) 5. GND (circle) 6. VCC 3 V 3 (circle) best regards, ryo
  22. Arty ethernet speeds

    The documentation for the arty indicates that it's capable of up to 100Mb/s with its ethernet. That appears to be a limit imposed by the TI phy used on the arty board. Presumably if a different phy were used, one that supports gigabit, the Artix itself is capable of supporting that speed?
  23. Arty hello world

    Hello to all, I'm a college student with a bit of arduino experience. I got ARTY because I have a course that requires learning the VHDL rudiments. (the choice of board was free, I hope I made a good choice!) My goal would be to start with a very simple project, maybe turn on some LEDs by pushing the buttons and getting familiar with the development environment. I am currently using Vivado 2017 and I have managed to have arty in the project board list. After that I do not know what to do, and I did not find a giuide for dummies that explained how to get to my goal. I have to use VHDL and for now my goal is to have a code as clean as possible and essential (also at the expense of not using all the potential of the board) I hope it is a not too complex and accessible request happy to start
  24. Hi there I am selling my Zinq-Z1 board ( zynq 7020 ) She is "as new". I put Arty Z7 in the title because these two board are so similar (not the same colour of pcb, and the Pynq has one thing more: a mic) mine is a pynq. My price is 99€ plus shipment , you can find easily on ebay my announce, there are some photos, I also sell on ebay my Spartan 6 board (papilio duo and computing shield) Thx & Regards B.
  25. Hello All, Have been attempting to enable interrupts on a project using the Arty and was running into issues with the intc_SelfTest failing. I loaded the Arty BSD from github thinking I had some issue with the project itself but am getting the same exact result. Any suggestions as to what I may need to change? I changed nothing in the BSD so I'm assuming it should be correct. Also followed multiple online tutorials and have been unable to solve the issue. All suggestions are greatly appreciated. Thx!