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  1. Hello, I checked the tutorials and read the pdf-s on the AXI Interrupt controller. However, i could use come clarification about a couple of things. In Microblaze advanced configuration there's an option to set interrupts to NONE/NORMAL/FAST, or leave it in AUTO mode. Is this setting linked to the AXI interrupt controller creation process? I mean if it run Block Automation, and enable Interrupt Controller, then AXI Interrupt Controller IP is created, but the setting doesn't change in the microblaze settings (for example it stays AUTO/NONE). Does that mean if i want a normal
  2. Hi, On my Arty A7 board i have the hello world running with Microblaze and UART. I added from the board tab the 4 buttons then i added the 4 LEDs. I'm using 2020.1, and by default it combined the AXI GPIO so there is a dual channel GPIO where both the leds and the buttons are connected. My problem is, that in Vitis the generated IO example code uses the same port, and only the buttons work... the device gets configured as such in the code: #define GPIO_OUTPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define GPIO_INPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID In xparameters.h i fou
  3. Hello. I believe similar questions are present on the forum before mine. But I specifically want to know aside from the peripherals difference (RAM, SDCard, VGA etc.), is it ideal to assume the HDL designs (except the peripherals IP) would be compatible with both of them if one is supported by some project. For instance, lowRISC has a guide based on Nexys for its core booting Linux (https://www.lowrisc.org/docs/untether-v0.2/fpga-demo) whereas SiFive E310 has been demonstrated on Arty. The LiteX project supports both the boards (at least from the code base it looks so). Can s
  4. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can
  5. Hi, I've got my Arty sending out UDP packets to my laptop, without any soft CPU involvement. I've still got to add checksums and so on, but at least it works! http://hamsterworks.co.nz/mediawiki/index.php/ArtyEthernet
  6. I am working with an Arty design and I have noticed that while I have no intra-clock timing failures, I still have high severity warnings in the "check timing" portion of my timing summary related to not having constraints for input and output delay (no_input_delay and no_output_delay). Does digilent provide suggested timings for the on-board peripherals (like Ethernet and flash), or do I have to go through all the datasheets myself and estimate the trace delay? I found this thread from 2017, but the question was never resolved.
  7. Hello, I am working through some of the examples for the Arty A7 device. The device seems to come pre-loaded with firmware, some simple reference design that makes use of UART, LED's and pushbuttons. Is there some project I can download to reproduce this reference design? I am planning to overwrite this in the future, but I also wanted to have a copy. Thanks
  8. Hi, I have done a project for ARTY board which uses a bootloader to run my software application following this tutorial: How To Store Your SDK Project in SPI Flash My problem is that it works only after I press the PROG botton. So, after I connect the power, the FPGA PL get programmed (I see LED blinking correctly), but it seems that the bootloader does not. Only after I press PROG it does. What should I do to avoid pressing PROG at the beginning? Thanks, Lorenzo
  9. elAmericano

    Artix7 & ZedBoard

    Hello, My group has acquired the two boards Artix A7 and ZedBoard for developing some applications. I am noticing couple differences regarding projects and documentation. One such difference has to do with the reference base design. For Artix A7 I am finding the PMOD ports, and I2C, SPI, UART, Ethernet included in Board connections. For ZedBoard, very few peripherals are included in the base design I was able to locate. Question: For developing new applications for Zynq, can you provide some information regarding Zynq base desing. Is there more complete project for i
  10. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store
  11. I have the Arty A7-100T and have successfully built and run a project using the PMOD RTCC module, which uses the I2C interface. I modified the project to use the I2C pins on connector J3 of the Arty and enabled the pullup resistors. I wired the SCL & SDA pins to the PMOD RTCC and all is good. It runs the same as if connected to the PMOD connector. So now I am trying to build my project without using the I2C defined port that is in the board definition files. I want to connect directly to the 6 control and data lines that make up the I2C port on the AXI IIC IP and I want to be
  12. Hello, I have combed through the forums but still have not found the answer I am looking for. I have the Arty board and Vivado 2015.4. I can create a project and I can select the Arty board in that process. I create a Block diagram on which to start building my 'circuit'. At this point I try two different ways to get a pmod port on the board: I click on the 'Board' tab and I find all the input and output ports (led, led_rgb, buttons, switches, spi, etc and Connector JA thu JD). I try and bring a JA onto the block diagram and get a message "Conn JA board component cannot be connecte
  13. i wanted to interface multiple digital serialiser with arty A7 35T board through pmod pins. And transmit the same data through UART. help me with the verilog code and other resource.
  14. Hi, First I tried with Nexys K7, here another try with Arty K7. There is now a great portfolio of Arty boards, spanning Spartan-7, Artix-7 and Zynq. The only thing missing is an Arty with a Kintex-7. And is seems imho well in reach, the XC7K70T is with ~$120 only $10 more expensive then the XC7A100T used on the Arty A7-100. So a Arty K7-70 should be possible at a reasonable price, slightly above the Arty A7-100. With that offer the Arty family would cover Arty S7 -- Spartan-7 and lowest cost Arty A7 -- Artix-7 Arty K7 -- Kintex-7 and highest speed
  15. Could I get voucher license having ARTY A7 board without one in the kit? I bought the new ARTY A7 but it doesn't have voucher license in the box. Thanks in advance)
  16. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io whi
  17. Hi all, I'm having trouble getting a spi module set to 'slave mode' to read data. I'm working with the Arty Board and attached is my Vivado block diagram. The SPI module that I'm having trouble with is 'axi_quad_spi_0'. I've set the IP to be in standard and unchecked Master Mode in the SPI Options. I set the FIFO to 256 and Freq Ratio 16x30. I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing. The other registers of axi_quad_spi_0 read as foll
  18. I went through the process of running MIG7 (Vivado 18.3) to generate a DDR3 controller for the Arty A7-100. I copied the digilent board files into the Vivado 18.3 board_files directory and chose arty-a7-100 when opening my project. When MIG7 starts, the first thing it wants is clock period. That's where I'm having the problem. MIG7 allows numbers between 2500 and 3300ps. But with my board, MIG7 won't allow any period less than 3225ps. That's a very narrow range of frequencies! I need to consider my FPGA general system clock speed in connection with making a high-speed UART for
  19. I am running Vivado 18.3 on Ubuntu 18.04, and cannot connect to my Arty board. While troubleshooting, I found directions on installing cable drivers and board files (https://reference.digilentinc.com/vivado/installing-vivado/start), however I cannot find the path referenced in 2.1. I have an /opt directory, but it is empty, and while I can find a couple /data directories that look like they could be correct, none of them contain a xicom (or .xicom) directory. Note: I installed Vivado a while back but never got around to playing with the board until now. I wanted to exhaust all options bef
  20. I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this: and looking at this diagram: Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output. But here is the usb_uart interface spec in the ./board_files/arty-a7-35/E.0/board.xml file : <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart"
  21. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for
  22. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by follo
  23. Hello, I am wondering what is the best way to share a big chunk of memory between two cores of Arty-Z7-10? Note that I have already gone through the XAPP1079 of Xilinx, however this tutorial does not really share the DDR memory between two cores. It only uses OCM to share a semaphore between two cores, so two cores can share the terminal. To give you more detail on what my goal is: I want to read a big chunk of data (something in oder of 15 - 30 MB) on CPU#0 and put that into DDR memory, and then let the CPU#1 know when I am done via a flag (which I know how to do with OCM). Followin
  24. Hello, I am trying to develop a simple verilog code on Arty-Z7-10 that writes to the SD card on the PL side, without having to use SDK software. To do so, I believe I need to setup my SD card pins as EMIO in the ZYNQ and modify the constraint file to uses correct pin mapping. However, I wonder if anyone has done such type of coding before and is able to provide me with more detailed information. I found this tutorial which has tried to do same thing with SPI, but it was not very detailed. https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part193
  25. Hello, I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue. Best, Mahdi