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Found 18 results

  1. Hi, Background: I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines. Question(s): I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how t
  2. Hi, I asked this on the Xilinx forums too, but so far no one has answered. Maybe someone here can help. I bought a arty-7z-20, so I could learn more about FPGA's. I downloaded Vitis+Vivado 2020.1, and followed some tutorials (for example this one https://nuclearrambo.com/wordpress/programming-the-zynq-7000-with-vivado-2019-2-and-vitis/) but they all have the same basic steps. The Vivado side is clear, I can generate a bitstream and export it to a board. I can also create the HDL wrapper, and export the xsa file. But now when I open Vitis, I should create a new platform project,
  3. Hi, I'm trying to boot petalinux from TFTP server and NFS root based on Arty Z7-20 Petalinux BSP Project (https://github.com/Digilent/Petalinux-Arty-Z7-20) Unfortunately, TFTP boot method is not included in the Project's README.md file. I found several useful infromation and tried them to my Arty-z7-20 board. [1] TFTP Boot and NFS Root Filesystems : https://elinux.org/TFTP_Boot_and_NFS_Root_Filesystems [2] Petalinux with Root NFS and Kernel on TFTP sever : https://www.youtube.com/watch?v=DHmcjkDDAlM [3] running netboot with u-boot-xlnx : https://forums.xilinx
  4. Hello, i have a problem with the Vivado SDK. I like to include some c Header: #include <stdio.h> #include <unistd.h> #include <stdbool.h> #include <string.h> #include <arpa/inet.h> #include <sys/select.h> #include <sys/socket.h> Eclipse tell me, that my includes are unresolved. I think that is because i have nearly thirty directories in my Vivado 2017.2 SDK Installation, but it is not defined what directory exactly should be used. Can anybody tell me what is the correct include path for a 32 bit Linux a
  5. Hi, I have been following the instruction on https://github.com/Digilent/Petalinux-Arty-Z7-20. These are well done and I got a running image on a SD card from the cloned git repo. Then I switched to the Digilent Apps description, changed some config and recreated the image. This one stopped after the message "Starting kernel..." After some tries, it turned out that just rebuilding the image even without any change leads to that behaviour. However, cleaning the build will again give a correct image. But I believe thats not the intention to clean for each build... What do I miss?
  6. Hello, you know, that i try to use uio. And i still got no result. Therefor i try the next Vivado 2018.1 with the still not delivered petalinux. I created a new Project in Vivado 2018.1 and i tried to choose the Arty-Z7-20 board. But i can't select it; before i did it, i copied the digilent board files into the Xilinx Directory. When do you provide the new board files for Vivado 2018.1; i Need the Arty-Z7-20 :-) Thank you...
  7. Hello, finally i was able to make a petalinux build with the BSP 2017.4 - so far, so good. Then i find out, which uio device is connected with the Arty-Z7-20 Buttons and switches. Both - the Buttons and also the Switches - are connected to one GPIO-IP-Core (Dual-Channel, all inputs). One AXI-GPIO has one base address and a dual channel GPIO has even only one base address. So the only way to address both channels is to use the base address offset for channel one and for channel two, isn't it? If i read channel one - which is assigned to the Buttons - then i can read the Buttons.
  8. Hello, i made the following design: You can see two GPIO Ports: - GPIO_RGB_LED, 3 Bit, Output only - GPIO_SW, two data bits plus one interrupt bit (e.g. Input clk), this port should throw Interrupts into the Linux App. After i build that design with Vivado, i used petalinux to create a Linux image. Here you can see the "/dev"-Folder which contains the installed Drivers: You can see three GPIO-Drivers. Now my question: In former questions i ask for the Driver Support in Linux and how i can write or use them. You told me, t
  9. I'm trying to build the Arty-Z7-20 petalinux project version 2017.4 but it keeps failing because off: libuio-1.0-r0 do_fetch libgpio-1.0-r0 do_fetch libpwm-1.0-r0 do_fetch gpiotil-1.0-r0 do_fetch pwmdemo-1.0-r0 do_fetch failing, because the connection times out, is there a way to bypass this?
  10. Hello, i have some errors while building the 2017.4 BSP based petalinux image. [email protected]:~/projects/2017.4/Arty-Z7-20$ petalinux-build [INFO] building project [INFO] sourcing bitbake INFO: bitbake petalinux-user-image Parsing recipes: 100% |##########################################| Time: 0:01:30 Parsing of 2473 .bb files complete (0 cached, 2473 parsed). 3266 targets, 226 skipped, 0 masked, 0 errors. NOTE: Resolving any missing task queue dependencies Initialising tasks: 100% |#######################################| Time: 0:00:06 Checking sstate mirror object a
  11. Hello, i have a new created petalinux project for the zynq processor (Arty-Z7-20). I'am not using a digilent bsp file to configure the project, because i have a simple selfmade design and i like to start with a minimalistic Linux. I like to support Linux pthread and sockets, thats all. If i implement a tcp/ip Server and if i use the select Routine to wait for incomming data then the "select" Routine does not return, even if i receive data. In an other thread here in this Forum i discuss a similar issue. There i have a Problem with the "uio" Interrupt handling, because the blocking re
  12. Hello, i have an other question: If i look in the Mouser electronic shop i see, that the zedboard is associated with digilent and you Show on https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ the board. Why do you have no support on https://reference.digilentinc.com/reference/software/petalinux/start for the zedboard? Thank you...
  13. Hello digilent, when do you update the Arty-Z7-20 examples and resources for this board? Could you please make at least two examples: One with Maximum Support of the given hw (all Features of Arty-Z7-20) and one Basic example which has the Chance two be compatible with future Vivado Versions? The Basic example should only be able to handle tcp/ip and uio, i would be very lucky. Thank you...
  14. Hello, is it true, that a device tree file like <finally-used-device-tree>.dts is always generic and will always generated thru a <source-for-device-tree-file>.dtsi file? I found some basic files in "/my-petalinux-project/components/plnx_workspace/" e.g. "zynq-7000.dtsi" and a generic "system-top.dts" file. Must i edit those files (e.g. zynq-7000.dtsi)? Is there an other relevant Location? Thank you...
  15. Hello, since now, i have only experience in debugging bare metal apps. I will write a linux tcp/ip-server, therefor i must be able to debug my c-code. I have tried the known bare-metal-workflow and instead of Chose "bare-metal" i Chose Linux as operating System. When i start the debugging process then i got the following error: What is a "Linux Agent" and why is it disconnected? Thank you...
  16. Hello, i used the "Arty-Z7-20-base-linux"-project with Vivado 2017.2, first i copied the board files to my new installed vivado 2017.2 Installation and then i run the "create_project.tcl" script. So far so good. After that i have tried to create a hdl-wrapper, because i liked to generate a bitstream. Vivado has got the following error: As you can see, the reason is: "IP definition not found" for the listed ip-cores (see error message). Can you tell me, what i should do? What is a "Petalinux-Arty-Z7-20-2017.2-2.bsp" file and what is it good for? Thank you...
  17. deppenkaiser

    Unknown Resource

    Hello, the online Manual wrotes: "[...] The Zynq presets file (available in the Arty Z7 Resource Center) takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length. [..]" Where are the files? What Name do they have? How do i use them? Thank you...
  18. deppenkaiser

    Where is J14?

    Hello, i'am still trying send "Hello World" to my terminal. I made a simple design in vivado and use the uartlite ip. But i cant generate the Bitstream because of undefined ports: "[DRC NSTD-1] Unspecified I/O Standard: 2 out of 132 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify a