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Hello, I am using Arty-Z7-10 board with 3 Pmods (NAV, GPS and RTCC), while there are only 2 JTAG ports available on the board. So, I decided to buy one of these 2*6-pin JTAG splitter cables and divide one of my JTAG ports between PmodGPS and PmodRTCC (since both of them need only one row of JTAG). Now, I am trying to make a block design and connect both of them to one JTAG, but it does not seem to be feasible. When I connect the first Pmod to the JTAG port, it occupies the whole port and it does not allow me to add another Pmod to it. Is this something I have to do in Verilog, and modify my XDC file? or is there an easier way to do it by just dragging and dropping the IPs in the block design? Best, Mahdi