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Found 24 results

  1. Tony_B

    Data acquisition

    Just looking for some help / advise / pointing in the right direction .. I need to capture some 16-bit parallel data from a sensor at about 10M samples / sec., accumulate it into blocks, and send the blocks out over a GigE link. The sensor data is going to be read from an external FIFO which will interface to my hardware. 1). Would an Arty Z4-20 be capable of this? .. or would something else be a better choice? 2). Assuming a Z4, any suggestions on topology? How would I best structure this? eg. I’m thinking DMA from GPIO to memory on the PL side, then Ethernet transfer from
  2. So just stopping by to say hello and that I'm excited to work on my Arty Z7 board. Looking forward to learning.
  3. Looking through the Arty Z7 documentation, I see that mostly it's about people running Linux on the embedded ARM. My application is more bare-bones. I'll need to write C code for the ARM including interrupt handlers. This needs to be real-time, so I can't afford the overhead of Linux running. In the reference manual, I see that "bare metal" programming on the ARM is possible. But I've not been able to locate any documentation for this. Have you got something I can read? I just want to make sure the job is not way too complicated before embarking on it. Thanks!
  4. Hello Everyone, I am trying to get my Arty Z7-20 (XC7Z020) to boot from flash with encryption enabled. If I do not enable encryption, I am able to get this to work. I am using the tool "Create Boot Image" in the Xilinx SDK. I open the encryption tab and check the box labeled "Use Encryption" and provide the "Part name." The Part name I use is "XC7Z020." I have also tried "XC7Z020CLG400", which I found when using that board in a Vivado project. The Boot Image is created just fine, and I am able to program the flash. However, when I power on the FPGA, the done light does
  5. I'm trying to build the Arty-Z7-20 petalinux project version 2017.4 but it keeps failing because off: libuio-1.0-r0 do_fetch libgpio-1.0-r0 do_fetch libpwm-1.0-r0 do_fetch gpiotil-1.0-r0 do_fetch pwmdemo-1.0-r0 do_fetch failing, because the connection times out, is there a way to bypass this?
  6. I just received the Arty Z7 board I ordered - it looked like a perfect mix of little Linux box, HDMI ports, and a big enough FPGA to implement some interesting video processing on. I assumed like previous Digilent products there would be a nice set of intro material - in particular, I'd assumed that there would be a SD card image I could burn and stick in the board and boot up into some preconfigured Linux environment that would let me load bitfiles into the FPGA and such. There appears to be... well, almost nothing. The "resource center" link on the product page goes to a stale Gith
  7. Hello! We have purchased a number of the Arty boards for some testing we are doing, and would like to be able to clear or reset any/all memory on board to the original state. -- Can Digilent provide a Statement of Volatility for the Arty Z7 and A7 (and original Arty if different from the A7)? -- For any non-volatile memory on these Arty boards, can Digilent provide a procedure to return the memory to the "fresh from Digilent" state? Thanks in advance! Jeff
  8. I have an Arty Z7 board which came with a Trenz EDDP kit for motor control. I need to use the Xilinx SDx development system to create some software for the board - in particular, FPGA bitstreams - but I can't figure out which (if any) of the Xilinx SDx zynq project types (microzed, zc702, zc706, zed, zybo) should be used, or whether I need to get a custom project type from somewhere. Any thoughts?
  9. Hello experts! I have an Arty Z7-20. For school projects I have to learn VHDL for FPGA programming, only for FPGA applications. What should I do to disable (inhibit) PS and to safely use PL only?
  10. I'm interested in purchasing the voucher for a node locked license of SDSoC. The description says it's locked to the Zedboard and Zybo. Is it locked to those particular boards or would the license work for the PYNQ and Arty Z7?
  11. Earlier this year I bought an Arty A7-35T and was able to create a project using Vivado and writing VHDL code. The thing that helped the most to get started was a blinking lights example project. Recently, I bought an Arty Z7-20 board, and would like to use it with SDSoC. I managed to get SDSoC installed and running. Now, how to start writing code? I've spent more than a day looking through various tutorials and getting started guides, but so far haven't found what I really need. One of the most helpful documents I found was the step-by-step "Introduction to the SDSoC Development Env
  12. Hello, I just got the Arty Z7 and I was trying the HDMI out demo. I followed the SDK handoff guide, downloaded the bitstream and run the demo. I can see the serial output and can enter commands, but I get a "no signal" on my monitor no matter the resolution. Checked and rechecked the connectors to no avail. I tested my monitor's HDMI input with the same cable on a raspberry pi and it works fine. I'm running Vivado/SDK 2016.4 on Xubuntu 17.1 Any ideas? Question 2: Is 1080p output really in spec for Z7? The zynq datasheet shows 950Mbps as the max fo
  13. Hi, I want to run simple DMA transfer (not using scatter gather) application program on the attached design. But the program is always hung when running XAxiDma_CfgInitialize(&AxiDma, Config) function. The JP4 jumper is set on QSPI mode and the running configuration mode is like the figure I attached. The same program is run and not hung on XAxiDma_CfgInitialize(&AxiDma, Config) if ran on ZYBO. But, with differences in run configuration mode. On ZYBO run configuration mode, I'm not using the initialization file and so not run the ps7_init. On Arty Z7 I need to use it, becaus
  14. Hi, if I wish to connect external push-buttons to IO ports (on Arty Z7-20) is it necessary to use also resistors or it will be nu problem to connect VCC to GND (1 to 0)?
  15. Hello everyone, I have been working in the arty z7, working to output HDMI video from a camera conencted by ethernet . While the ehternet hardware, driver and code are fully functional. I have yet to make the hdmi function on the OS. Currently, i have follow succesfully the following tutorial, that means that i have the hardware for HDMI in and out and can use through the provided Bare metal application. Now, i have to move this functional hardware form a bare metal application to a OS application, for that i need some drivers to control the Axi Stream conected to th
  16. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  17. Hi all, have read previous postings, none of them answered my problem. I am using an Arty Z7 20, Vivado 2017.2 and latest board files (A.0). I have walked through the Zybo getting started with Zynq tutorial, using the Arty Z7 board settings. My block design contains Z7 PS, PS reset, AXI Interconnect and AXI GPIO (btns_4bits). Block design validates ok and can create HDL wrapper, create bitstream, export hardware and launch the SDK. I've selected the "Hello World" example and am trying to get it running. The cable appears to be connected ok and JP4 is set to QSPI.
  18. Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [[email protected] Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statisti
  19. skaat27

    Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  20. Where can I see the relations between the Arty Z7 board pins (I/O) and the FPGA pins? In "Arty Z7 Reference Manual" it is not enough information: only buttons, slide switches, LEDs and HDMI pins relations appear. (eg. BTN0 is D19) What about the rest of the pins (I/O)?
  21. Hello, I run the demo, which works fine for me, as long I am using the default 1024x720 resolution. Changing the resolution to 1280x1024 (60 Hz) the demo is not able to detect the signal from the input signal ("!HDMI UNPLUGGED!"). All hdmi out resolutions work fine. How can I fix this issue? Where should I start? Thanks climblinne
  22. Hi, I've got some error while trying to download .elf file to Arty z7-7020. The error I get is like this An internal error occurred during: "Launching New_configuration". No Target with ID 64 in the System ERROR : Unexpected error while launching program. java.lang.RuntimeException: Failed to download ELF file AP transaction error (DP CTRL_STAT=0xf0000021) Error Address = 0x00100000, Size = 0x00000004 at com.xilinx.sdk.targetmanager.internal.TM.downloadELF( at
  23. I tried to get the samples "HDMI_IN" & "HDMI_OUT" running with Vivado 2016.4. First there is no top module name set, when generating the project file. After fixing this, there are unspecified ports. ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 7 out of 145 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which i
  24. I just received my Arty Z7! I'm trying to get a basic example up and running. Since there aren't any tutorials up yet on the Arty Z7 start page: so I tried to follow the "Getting Started with Zynq" example for the Zedboard: I created the project using the Arty Z7 20 Vivado board files. Everything went smoothly until I try run the code example (Launch on Hardware). I get: ERROR : Me