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Found 8 results

  1. Hello, I have a Digilent ARTY Z7-20 Board. I could program the S25FL128SAGMFI001 QSPI FLASH on the board. But unfortunately one day while I was programming the flash, a friend of mine accidentally pressed the RESET button the board. After that, I could not program the FLASH anymore. I have copied the console output. I would be happy, if someone could help me. I really need to program the FLASH. Is the FLASH broken after this accident. Would a replacement of the FLASH if I replaced it with a new one? Kind Regards Kerem OKTEM cmd /C program_flash -f \ D:\ .... .sdk\FSBL\bootimage\BOOT.mcs \ -offset 0 -flash_type qspi-x4-single -fsbl \ D:\ .... .sdk\FSBL\Debug\FSBL.elf \ -blank_check -verify -cable type xilinx_tcf url TCP: ****** Xilinx Program Flash ****** Program Flash v2019.1.3 (64-bit) **** SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. WARNING: Failed to connect to hw_server at TCP: Attempting to launch hw_server at TCP: Connected to hw_server @ TCP: Available targets and devices: Target 0 : jsn-Arty Z7-003017A702C7A Device 0: jsn-Arty Z7-003017A702C7A-4ba00477-0 Retrieving Flash info... Initialization done, programming the memory ===== mrd->addr=0xF800025C, data=0x00000001 ===== BOOT_MODE REG = 0x00000001 WARNING: [Xicom 50-100] The current boot mode is QSPI. If flash programming fails, configure device for JTAG boot mode and try again. ===== mrd->addr=0xF8007080, data=0x30800100 ===== ===== mrd->addr=0xF8000B18, data=0x80000000 ===== Downloading FSBL... Running FSBL... Finished running FSBL. ===== mrd->addr=0xF8000110, data=0x00177EA0 ===== READ: ARM_PLL_CFG (0xF8000110) = 0x00177EA0 ===== mrd->addr=0xF8000100, data=0x0001A008 ===== READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008 ===== mrd->addr=0xF8000120, data=0x1F000400 ===== READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000400 ===== mrd->addr=0xF8000118, data=0x00177EA0 ===== READ: IO_PLL_CFG (0xF8000118) = 0x00177EA0 ===== mrd->addr=0xF8000108, data=0x0001A008 ===== READ: IO_PLL_CTRL (0xF8000108) = 0x0001A008 Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000. ===== mrd->addr=0xF8000008, data=0x00000000 ===== ===== mwr->addr=0xF8000008, data=0x0000DF0D ===== MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D ===== mwr->addr=0xF8000910, data=0x000001FF ===== ===== mrd->addr=0xF8000004, data=0x00000000 ===== ===== mwr->addr=0xF8000004, data=0x0000767B ===== MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B U-Boot 2019.01 (Jun 04 2019 - 09:48:11 -0600) Model: Zynq CSE QSPI Board DRAM: 256 KiB WARNING: Caches not enabled In: dcc Out: dcc Err: dcc Zynq> sf probe 0 0 0 Warning: SPI speed fallback to 100 kHz SF: unrecognized JEDEC id bytes: ff, ff, 00 Failed to initialize SPI flash at 0:0 (error -2) Zynq> ERROR: [Xicom 50-186] Error while detecting SPI flash device - unrecognized JEDEC id bytes: ff, ff, 00 Problem in running uboot Flash programming initialization failed. ERROR: Flash Operation Failed
  2. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY. A few questions come to mind: Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors... Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.
  3. MVS

    Arty Z7-20 Serial Com

    Hello everyone, I bought an Arty z7-20 board a month ago and my first project depends on serial communication. I made a program in VHDL but I could not know which are the pins that I should assign to the uart. From schematic file, i understand that i have to comunicate the fpga with the pins C5 and C8, for Tx and Rx, on the chip bank500, but.... i dont see what are the pins to enable uart in the .xdc master file to do this. A lot of thanks for share your experience! I leave here a simple design to taste the uart. The idea is that the fpga recive a data and send it back to a terminal. SERIAL_ENSAYO.vhd
  4. zazou

    HDMI_IN Arty Z7-20 ERROR

    Bonjour, J'ai testé le code du projet HDMI_IN publié sur le GitHub d'ici sur la version 2016.4 de Vivado et j'ai eu cette erreur ! any Help !
  5. Bonjour, je travail cette période sur le hdmi_out de la carte fpga arty z7-20, et comme tout le monde j'ai commencé par télécharger le fichier tuto de .git, deja apres l'implémentation y a rien qui s'affiche sur le deuxieme écran donc j'ai essayé de modifier les blocs IP par l'ajout d'un bloc qui convertit une image à une matrice et le lié avec le reste des blocs en appliquant les modifications nécessaires sur le BD et le .vhd , finalement, j'ai obtenue cette erreur. Remarque à savoir : j'ai vérifié les liaisons en RTL design et elles me paraits correctes MErci pour vos aides, translated by google translate by JPEYRON Hello, I work this period on the hdmi_out of the art7 zp-20 fpga card, and like everyone else I started by downloading the .git tutorial file, already after the implementation there is nothing that appears on the second screen so I tried to modify the IP blocks by adding a block that converts an image to a matrix and binds it with the rest of the blocks by applying the necessary modifications on the BD and the .vhd, finally, I got this error. Note: I checked the links in RTL design and they seem correct to me MErci for your help,
  6. Bonjour à tous, mon projet à pour but de communiquer ma carte Arty z7-20 avec le ship TLC5940 afin de pouvoir allumer des Leds RGB, donc pour commencer je me demande est-ce que c'est faisable ? et quels sont les pistes que je devrai suivre ? MErci en avance (translated by JColvin via Google Translate): Hello everyone, my project aims to communicate my card Arty z7-20 with the ship TLC5940 in order to light RGB Leds, so to begin I wonder is it feasible? and what are the tracks that I will have to follow? Thank you in advance
  7. Hello All, Today i received my Arty Z7-20 and i wanted to install the vivado software. I have confusion here on software toll version. Example projects are build on 2016.4 and planned to install 2017.4 V (latest version). Do you see any problem?
  8. Good day, I'm a MEng Student and I want to participate at Digilent Design Contest 2017. The organizers suggested me choosing a development board specified in their list which includes Arty Z7-10 and Arty Z7-20 (they also suggested me to contact Digilent for more information regarding the availability of these two development platforms). In a few days, I need to decide which development board I'll use for the contest (I specify the model of the board and they will handle the purchase process). My question is: Is either of Arty Z7-10 or Arty Z7-20 available at the moment? (at least for a candidate for Digilent Design Contest 2017)? Thank you in advance!