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Found 5 results

  1. I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this: and looking at this diagram: Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output. But here is the usb_uart interface spec in the ./board_files/arty-a7-35/E.0/board.xml file : <interface mode="master" name="usb_uart" type="" of_component="usb_uart" preset_proc="uart_preset"> <preferred_ips> <preferred_ip vendor="" library="ip" name="axi_uartlite" order="0"/> </preferred_ips> <port_maps> <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out"> <!--Change to “in”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_txd"/> </pin_maps> </port_map> <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in"> <!--Change to “out”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_rxd"/> </pin_maps> </port_map> </port_maps> </interface> So, usb_uart_txd should be "in", usb_uart_rxd should be "out". When I change this, the UartLite serial port works! I tried to change the direction of the pins in the Project HDL "wrapper" to no avail. Please note that this default config is found in the board.xml files for arty, arty-A7 and arty-S7. Do the board.xml files need to be changed? Is there some other way to change pin direction in the Vivado Project?
  2. tl;dr: If I use a 12v external power supply on my Arty-S7-50RevE can I use VIN (& GND) to power a 0.1A, 12v cpu fan? Longer: I'm having heat issues with my soft CPU on the S7 and so want to cool it before I take it multi-core. I've installed a heatsink (from here I've got a nice CPU fan left over from another project which fits my arty project well. However the fan is 12v. But I'm already powering the board with a external coaxial 5A 12v supply. Looking at the manual you can also power it via VIN (J8-8) instead - and if you look at the diagram VIN is just connected straight to the v-external power supply*. This seems to mean I should be able to treat VIN as a 12V output and directly connect the 12v cpu fan to it. Is this something which is acceptable? (I tried it and it seems to work fine) thanks mike * see Figure 1.1 here:
  3. icedefender

    Arty S7 step file

    I have found the step file for Arty board, but not for the Arty S7 board BTW the Arty borad looks great, I just need one for Arty S7 I would also like to get a 3d step file for "Pmod Clip: Mechanical Mount for Pmod boards" SKU: 240-107
  4. Hello, I want to download Xilinx bit file from Raspberry Pi to Arty S7, and adept utility for ARM seems to be the solution for it. So, I tried the following steps and it almost seems to work except the last step. I used the same bit file with Adept System on Windows, so bit file seems to be fine, and I'm suspecting if the adept utility needs some kind of update for the database. I'm currently using digilent.adept.runtime_2.16.6-armhf.deb and digilent.adept.utilities_2.2.1-armhf.deb. Any advice will be appreciated. Thanks, Taehyun root@raspi:/home/arty# djtgcfg enum Found 1 device(s) Device: ArtyS7 Product Name: Digilent Arty S7 - 50 User Name: ArtyS7 Serial Number: 210352A6C0F8 root@raspi:/home/arty# djtgcfg init -d ArtyS7 Initializing scan chain... Found Device ID: 0362f093 Found 1 device(s): Device 0: XC7A ? T root@raspi:/home/arty# djtgcfg prog -d ArtyS7 -i 0 -f main.bit ERROR: failed to set programming file
  5. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to 4 LEDs on the board. The purpose is to monitor the high nibble of a 32-bit ALU calculation using the LEDs on the Arty board. The design works under behavioral simulation, and it elaborates correctly (see attached schematic of the elaborated design). However, when I synthesize the design, it is reduced to almost nothing -- with the clock and reset pins routed nowhere, and the LED pins routed to some buffers connected to ground. The entire internals of the design are removed (see included schematic of the synthesized design). Can anyone help me figure out why this is happening? Here are the sources of the upper levels of the design, and the relevant constraints that I've applied for the FPGA board: SOURCES: ---------------- -- pindelivery.vhd -- Routes package pins to logical units library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity pindelivery is Port ( clk_in : in STD_LOGIC; rst_in : in STD_LOGIC; leds_out : out STD_LOGIC_VECTOR (3 downto 0)); end pindelivery; architecture behavioral of pindelivery is component topLevel_debug port (clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector(3 downto 0)); end component; signal rst_out : std_logic := '0'; begin rst_out <= not rst_in; tld1 : topLevel_debug port map (clk => clk_in, rst => rst_out, led_out => leds_out); end behavioral; ---------------- -- topLevel_debug.vhd -- Top-level module for debug library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity topLevel_debug is port ( clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector (3 downto 0)); end topLevel_debug; architecture behavioral of topLevel_debug is component controlTest port (clk : in std_logic; rst : in std_logic; r0_highnibble : out std_logic_vector(3 downto 0)); end component; begin cpu1 : controlTest port map (clk => clk, rst => rst, r0_highnibble => led_out); end behavioral; ---------------- CONSTRAINTS: ---------------- ## Clock signal set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { clk_in }]; ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { leds_out[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { leds_out[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Reset button set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { rst_in }]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property INTERNAL_VREF 0.675 [get_iobanks 34] ---------------- Any assistance would be much appreciated! Thanks, Curt Pehrson