Search the Community
Showing results for tags 'arty ddr3'.
Hi, I am new to the FPGA world and have just purchased an Arty dev kit from Farnell. I received a rev C Arty, which I thought was the current revision, only to find when I got started that it is an older board that has since been replaced by the Arty A7 rev E. My question is, is the Arty rev C "Arty-Master.xdc" file (which actually says Rev B on the first line!) compatible with the current Vivado 2020.1 build? If not, which XDC file(s) should I be using? The reason I ask is that I've been trying to include the DDR3 block from the board package but Vivado throws a couple of err
I'm trying to compile the Xilinx example file for the MIG generated DDR3 controller in Vivado 2015.4. I used the .ucf file to generate the controller just fine. But when I look at the .xdc file, I don't see the DDR3 pins. I see all the other interfaces I believe, except for the DDR3. Won't this prevent a design that uses the DDR3 from compiling?