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Found 6 results

  1. I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this: and looking at this diagram: Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output. But here is the usb_uart interface spec in the ./board_files/arty-a7-35/E.0/board.xml file : <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset"> <preferred_ips> <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/> </preferred_ips> <port_maps> <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out"> <!--Change to “in”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_txd"/> </pin_maps> </port_map> <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in"> <!--Change to “out”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_rxd"/> </pin_maps> </port_map> </port_maps> </interface> So, usb_uart_txd should be "in", usb_uart_rxd should be "out". When I change this, the UartLite serial port works! I tried to change the direction of the pins in the Project HDL "wrapper" to no avail. Please note that this default config is found in the board.xml files for arty, arty-A7 and arty-S7. Do the board.xml files need to be changed? Is there some other way to change pin direction in the Vivado Project?
  2. mhampson

    Arty A7 Rev C Schematic

    Where can I find the Rev C schematic for the Arty A7? The only link I can find does not apply to my board.
  3. For the ARTY A7 - 35T board, it possible to choose a clock in the constraints file that is greater than 100MHz?
  4. Hello. I plan to purchase an Arty A7 for my project. I wondering what is the function of the plated-through hole that locate beside R225 (red circled in diagram below). Thank. Beng Liong
  5. Ignacas

    FPGA audio - ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 (24bit@48k), I2S output. DAC will be CS4390 (24bit@48k), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  6. Hello! We have purchased a number of the Arty boards for some testing we are doing, and would like to be able to clear or reset any/all memory on board to the original state. -- Can Digilent provide a Statement of Volatility for the Arty Z7 and A7 (and original Arty if different from the A7)? -- For any non-volatile memory on these Arty boards, can Digilent provide a procedure to return the memory to the "fresh from Digilent" state? Thanks in advance! Jeff