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Found 12 results

  1. In all example project I could found, rgb_led is driven from a GPIO block. That works well but I need to drive it from a row of XOR gates and so far I could not convince Vivado to connect the output of the XOR to rgb_led. If you look at the attached picture, the goal is to connect "Res" or "BUFG_O" to rgb_led (which seems to have a 12 bit input since the GPIO which was driving it in the sample project is 12 bit wide). Does anyone know how to do ?
  2. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  3. Hello, for my project, I would need to physically access pins BDBUS2 and BDBUS3 of the FTDI FT2232 chip on Arty A7 board. I understand that the circuit part around the FT2232 chip is proprietary and not part of the released schematic. Is there any pin/pad on the board that would allow me to physically access these signals (i.e. solder there a piece of thin wire)? Or would I need to solder wires directly onto the pins of the FTDI chip? Note: I do not yet have an Arty A7 board at my disposal so cannot investigate the physical connection myself. Thank you, regards Jan Matyas The below picture is taken from the FT2232H datasheet (
  4. Hi, I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB. This differential signal will be an input to a buffer on the FPGA. The current xdc file on github uses LVCMOS33 as a default standard as shown below. set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] Would it be fine if I use LVCMOS33 or should I use another IO standard and if so which one should I use. I am using the Arty A7 100t board. Thank you
  5. I'm trying to integrate a custom IP module (AXI4 peripheral) with the Vivado IP Integrator flow on the Arty-A7 board. I've followed the tutorial outlined here: I am able to successfully generate a bitstream - my PWM signals should be wired out to the PMOD JB connector. However, nothing works once I try to launch an application from within SDK. Even something as simple as "Hello World" fails to run. The board support package, libraries, and applications all compile without issue. The kicker is that as soon as I revert back to the design WITHOUT the custom IP module, everything works fine and I can run applications from within SDK. Below are screenshots of my block diagram and constraints file. The constraints file only contains the additional information required for the PWM signals, assuming all the rest of the constraints are pulled in from the board file like they are when the custom IP module is not part of the design. Thoughts??? Using Vivado 2017.4
  6. Hi. I am new to Vivado platform / Digilent's Arty board. I am trying to get Microblaze to work with Axi timer to trigger interrupt at a certain rate. The image below shows the overall architecture. The board is successfully talking via UART and I can print on Terminal. I compiled the code below and no error came up; I ran the program but the interrupt is not triggered at all. #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xintc.h" #include "xtmrctr.h" #include "xparameters.h" #include "xil_exception.h" #include "xstatus.h" XTmrCtr TimerCounterInst; XIntc InterruptController; #define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID #define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID #define TMRCTR_INTERRUPT_ID XPAR_INTC_0_TMRCTR_0_VEC_ID #define TIMER_CNTR_0 0 #define RESET_VALUE 500000 void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber); //static int count = 0; volatile int TimerExpired; int main() { /* Initialization */ XStatus status; // 1. Platform init_platform(); print("Platform initialized \r\n"); // 2. Timer Counter status = XTmrCtr_Initialize(&TimerCounterInst, TMRCTR_DEVICE_ID); if (status != XST_SUCCESS){ print("Timer counter initialization failed \r\n"); return status; } print("Timer counter initialized \r\n"); // 3. Interrupt status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID); print("Interrupt initialized \r\n"); status = XIntc_Connect(&InterruptController, TMRCTR_INTERRUPT_ID, (XInterruptHandler)XTmrCtr_InterruptHandler, (void *)&TimerCounterInst); if (status != XST_SUCCESS){ print("Interrupt connect failed \r\n"); return status; } print("Interrupt set up \r\n"); // 4. Interrupt Start status = XIntc_Start(&InterruptController, XIN_REAL_MODE); if (status != XST_SUCCESS){ print("Interrupt start failed \r\n"); return status; } XIntc_Enable(&InterruptController, TMRCTR_INTERRUPT_ID); Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XIntc_InterruptHandler, &InterruptController); Xil_ExceptionEnable(); // 6. Timer Counter Handler XTmrCtr_SetHandler(&TimerCounterInst, TimerCounterHandler, &TimerCounterInst); print("Timer counter handler set \r\n"); // 7. Timer Options XTmrCtr_SetOptions(&TimerCounterInst, TIMER_CNTR_0, XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION); print("Timer options set \r\n"); XTmrCtr_SetResetValue(&TimerCounterInst, TIMER_CNTR_0, RESET_VALUE); print("Timer reset value set \r\n"); // 8. Timer Start XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_0); print("Timer start \r\n"); print("ALL PASS \r\n"); while(1){ //DO NOTHING FOR NOW } cleanup_platform(); return 0; } void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber){ XTmrCtr *InstancePtr = (XTmrCtr *)CallBackRef; print("IN TIMER\r\n"); if (XTmrCtr_IsExpired(InstancePtr, TmrCtrNumber)){ print("Expired\r\n"); } } But when I ran the self test after initialization of XTmrCtr, it actually does not pass the test with a status of 1 (which is indicated as failure in xstatus.h as #define XST_FAILURE 1L) status = XTmrCtr_SelfTest(&TimerCounterInst, TMRCTR_DEVICE_ID); if (status != XST_SUCCESS) { xil_printf("Timer self-test failed: %d \r\n", status); return XST_FAILURE; } print("Timer self-test pass \r\n"); If I understand correctly, the self-test is to check if the hardware is set up correctly. I don't know where in the block design side is wrong. I am using following setup: 1. Clock wizard with 166.667 MHz and 200MHz 2. DDR3 SDRAM that takes in 166.667MHz as sys_clk and 200MHz as ref_clk 3. Microblaze with a separate clock [mig_7series/ui_clk (83MHz)] 4. UARTlite (interrupt connected to axi_intc via microblaze_0_xlconcat) 5. Axi Timer (interrupt connected to axi_intc via microblaze_0_xlconcat) I would appreciate your help! Please let me know if you need any other information. Thanks!
  7. I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this: and looking at this diagram: Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output. But here is the usb_uart interface spec in the ./board_files/arty-a7-35/E.0/board.xml file : <interface mode="master" name="usb_uart" type="" of_component="usb_uart" preset_proc="uart_preset"> <preferred_ips> <preferred_ip vendor="" library="ip" name="axi_uartlite" order="0"/> </preferred_ips> <port_maps> <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out"> <!--Change to “in”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_txd"/> </pin_maps> </port_map> <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in"> <!--Change to “out”--> <pin_maps> <pin_map port_index="0" component_pin="usb_uart_rxd"/> </pin_maps> </port_map> </port_maps> </interface> So, usb_uart_txd should be "in", usb_uart_rxd should be "out". When I change this, the UartLite serial port works! I tried to change the direction of the pins in the Project HDL "wrapper" to no avail. Please note that this default config is found in the board.xml files for arty, arty-A7 and arty-S7. Do the board.xml files need to be changed? Is there some other way to change pin direction in the Vivado Project?
  8. mhampson

    Arty A7 Rev C Schematic

    Where can I find the Rev C schematic for the Arty A7? The only link I can find does not apply to my board.
  9. For the ARTY A7 - 35T board, it possible to choose a clock in the constraints file that is greater than 100MHz?
  10. Hello. I plan to purchase an Arty A7 for my project. I wondering what is the function of the plated-through hole that locate beside R225 (red circled in diagram below). Thank. Beng Liong
  11. Ignacas

    FPGA audio - ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  12. Hello! We have purchased a number of the Arty boards for some testing we are doing, and would like to be able to clear or reset any/all memory on board to the original state. -- Can Digilent provide a Statement of Volatility for the Arty Z7 and A7 (and original Arty if different from the A7)? -- For any non-volatile memory on these Arty boards, can Digilent provide a procedure to return the memory to the "fresh from Digilent" state? Thanks in advance! Jeff