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Found 3 results

  1. I'm trying to build a design for the Arty A7-100 (not using MicroBlaze), using the AXI Quad SPI memory for user data (and also for bitstream storage). The Reference Manual (and the master .xdc file) mention six external pins for this (actually the .xdc file only mentions five). But when I select the Arty A7100/External Memory/Quad SPI Flash from the "Board" window, it gives me a block for which the SPI_0 interface has 18 pins. Essentially each data pin has become three (_i, _o and _t). Am I supposed to put IO buffers there myself, or have I somehow got the wrong block? If so, please would someone point me to the right package? Thanks
  2. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  3. elAmericano

    ESP32

    Hello, I am working on integrating ESP32 PMOD into a vivado 2018.2 project. I have imported DIgilent IP library into Vivado. When I place PMOD and connect to board, during compilation. It is actually a general message from the block design (See attached image). It apperas to me that this IP is for ArtyZ7? or some other Zync product? If so, is there IP available for Arty A7 or is this message to be ignored?