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  1. I tried to build the XADC example project using Arty-Z7-20-xadc-2016.4-2.zip , https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-xadc-demo/start , and https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start . Using Vivado 2016.4, after entering the tcl command "source ./create_project.tcl" I get ...# update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2406] Cannot identify part xc7a200tsbg484-1 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7a15ticsg324-1L ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' (etc.) Using Vivado 2017.4, I get a lot farther. I clicked Generate Bitstream. While launching implementation run, I got a critical warning: [IP_Flow 19-4739] Writing uncustomized BOM file 'c:/Users/janko/Xilinx/Arty-Z7-20-xadc/src/ip/xadc_wiz_0/xadc_wiz_0.xml' The build subsequently failed. I found an answer (AR# 69645) on the Xilinx site related to the IP_Flow 19-4739 warning, but it wasn't helpful. There is indeed a file C:\Users\janko\Xilinx6\Arty-Z7-20-xadc\src\ip\xadc_wiz_0\xadc_wiz_0.xci (and nothing else) in that directory, but removing that file (as the AR suggests) doesn't help. How can I build this example project?