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Found 22 results

  1. Objective: Transmission of Non-MIPI camera sensor data (i.e. any monochrome sensor) using MIPI CSI-2 TX Controller Ip core from on one Arty7 Board to another Arty7 board as MIPI CSI-Rx system or any MIPI Receiver based Video processor. IP core Application: The Xilinx MIPI CSI-2 TX Controller implements camera sensor transmitter interface over MIPI D-PHY Interface. It can be used to bridge between non-MIPI camera sensors to MIPI based video processor. This Core provides combination of MIPI CSI-2 transmit controller and D-PHY interface. System Overview as per our understandi
  2. Hi, On my Arty A7 board i have the hello world running with Microblaze and UART. I added from the board tab the 4 buttons then i added the 4 LEDs. I'm using 2020.1, and by default it combined the AXI GPIO so there is a dual channel GPIO where both the leds and the buttons are connected. My problem is, that in Vitis the generated IO example code uses the same port, and only the buttons work... the device gets configured as such in the code: #define GPIO_OUTPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define GPIO_INPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID In xparameters.h i fou
  3. elAmericano

    pmod esp32

    Hello, I am working with Artix A7 board, implementing various PMODs successfully. I am having some issue with PMOD-ESP32 unfortunately. The source files from a project off github (ESP32.c/ESP32.h) from https://github.com/mitchellorsucci/PMODESP32 as well as the included libraries (PmodESP32.c/PmodESP32.h) GitHub Project: I believe the following macros need to be re-defined in the ESP32.h file from github, however in XILINX project for Artix A7, there is a uart-lite that is connected via AXI and there is a uart connected to the ESP32 IP. I have tried to define both. When
  4. elAmericano

    Artix7 & ZedBoard

    Hello, My group has acquired the two boards Artix A7 and ZedBoard for developing some applications. I am noticing couple differences regarding projects and documentation. One such difference has to do with the reference base design. For Artix A7 I am finding the PMOD ports, and I2C, SPI, UART, Ethernet included in Board connections. For ZedBoard, very few peripherals are included in the base design I was able to locate. Question: For developing new applications for Zynq, can you provide some information regarding Zynq base desing. Is there more complete project for i
  5. Hello, I am using Arty7 board and I am strugglling with DDR3 RAM in Microblaze. I added to my design UART core Mig7 series core. Also, I have data set to write the DDR3 RAM after writing operation I will read these data set. Unfortunately, I couldnt upload into the DDR3 ram that data set. How can handle with thise issue? Can you help me?
  6. I am learning to use DMA in Scatter Gather mode. So i use example code ("xaxidma_example_sg_poll.c"). Using "xil_printf" function to see value, I am done with this but it only transmit 1 BD, and i want more. I edit "SendData" function like this to transmit 2 BDs. // i edit this code to transmit more than 1 BD static int SendPacket(XAxiDma * AxiDmaInstPtr) { XAxiDma_BdRing *TxRingPtr; u8 *TxPacket; u8 Value; XAxiDma_Bd *BdPtr; int Status; int Index; TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr); /* Create pattern in the packet to transmit */ TxPacket = (u8 *) Packet; Value = TE
  7. Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.
  8. elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator module.it is not taking any inputs according to the module. thanks elevator12.txt
  9. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  10. How to connect the pins in the nexys4 artix7 temperature sensor
  11. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different k
  12. Hi, I've a requirement to interface a CMOS Image sensor(MT9P006) with Artix7 FPGA. I've to perform image processing including autofocus and interfacing with USB 3.0 peripheral controller IC. Is it possible with artix7??? If yes, then what are the tools (like vivado ISE etc) required and what will be the expected cost for those tools... Is there any free software alternatives for them??? Thank you...
  13. Hello, I have a code that interface keyboard to display scan code. I have wireless keyboard that doesn't respond when I press key, while wire or old style keyboard work just fine. the keyboard model is logitech k400r
  14. Manas

    XADC demo

    Hi I have tried to execute the xadc demo code but keep getting the same error every time.Due to this error I'm unable to generate the bit file. Please help me solve this issue. Regards
  15. Hi, I'm trying to use xadc demo project to read sensor output and perform necessary action based on the xadc output. I'm getting the digital output when some analog signal is fed to the ports A18 and B18 of artix7. I'm stuck as how convert the values to ppm value so as to generate a warning system. Hope someone can help. Regards Manas
  16. I ran speech simulation (analog) on Matlab, and here is the code and result. I want create an analog stimulus file for UNISIM for XADC execution on Xilinx Vivado. I use Vivado 2015.4 with board Artix7 (xc7t35cpg236 - 1C). 1. How to make an analog stimulus file using these information? I will need Time(ns), VAUXP(V), TEMP, VCCINT, VCCAUX, VCCBRAM values. 2. How many set of readings can I take? 3. Should the time be in millisecond, nanoseconds or seconds? Please find attached 'SIM_MONITOR_FILE' saved in data.xls and the simulation file for word 'Jam', obtained u
  17. Hello all, Can anyone help me in Basys 3 project? I am trying to interface Analog Sensor to Basys3 XADC pin. I am trying to use the sample code given wiki basys3. Priority: 1) Where do we change in given code for any specific XADC pin. I could not find any 'pin' definition in behavior code. Why there are some IP code files there? It is not UART though. 2) How to generate PWM for Servo motor?
  18. FPGAist

    Nexys4 Altium sources

    Hi, I would like to get the Altium schematics sources for the Nexys4 Artix7 board. Thanks!
  19. Hi, I'm trying to read the Configuration Flash of the Nexys4DDR. I need to achieve a relatively high speed. Here is a short summary of what I'm trying to do: My design will be controlled by an external master and there is no way to delay the masters request. The start address is latched first. After that I have about 1 us until the first read request will be applied. The subsequent reads will occur in a burst with a read cycle time of about 350 ns. Each read must deliver 16 bits of data to the master. I've been thinking about the QSPI-Flash as some kind of boot rom. And now I'm trying out if
  20. ntallen

    Nexys4 Spi Flash

    In section 3 of the Nexys4 manual, it says: An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data. I spent some time trying to figure out how to accessthat available space but was thwarted by the fact that the configuration clock output at E9 is dedicated for use during FPGA configuration, so I can't drive it in my design to access the flash. Is there a work around for this that would actually make it possible to access this extra space?
  21. Syaoran74

    Vmod+nexys 4

    Hi all, I am a 4th year engineering student from RMIT university of Australia. I'm in the search for FPGA board for the purpose of generating a depth map via stereo cameras, as part of a larger project. What has caught my eye is the Nexys4-DDR board primarily for its Xilinx Artix-7 chip and upon further searching the Digilent store i so found the VmodCAM module which may be particularly useful for the project. However i am aware as to the fact that the Nexys4 board does not have a VHDCI port and hence would like to know of any work arounds to this issue, possible PMOD cameras or other ways
  22. This question was posted by Daedronus on the Nexys4DDR youtube video: Artix 7 can output directly hdmi video, why bother wasting IOs for the rather poor 12bit vga?