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Found 7 results

  1. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx
  2. We are suppose to add a library from here: https://github.com/Digilent/vivado-library/releases and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  3. Hi, I have been looking on the Digilent site for a while now but I haven't found what the maximum operational temperature of the Nexys Video board is. I use the board to test another in house developed board but I need to run a thermal test at 60°C. Is this possible with the Nexis Video? Kind regards, Oceley
  4. Flux

    Nexys Video HDMI Capabilities

    Hello, I'm trying to understand the HDMI capabilities of the Nexys Video Artix-7. I don't own a board yet, so these queries are based on reading spec sheets; please excuse any errors or omissions on my part. The FPGA on the Nexys Video is XC7A200T-1SBG484C, which supports 4 GTP transceivers at 3.75 Gbit/s [1]. However, based on my best interpretation of the Nexys Video data sheet [2] the HDMI ports aren't using the GTP transceivers. The GTPs are used for DisplayPort and FMC connector. Given the HDMI ports aren't using the GTPs, what is the maximum data rate the FPGA can support for them? The HDMI input has an Analog AD8195 buffer, which supports 2.25 Gbps data rate [3]. The HDMI output has a TI TMDS141 buffer, which also supports a 2.25 Gbps data rate [4]. This seems to limit the Nexys to 720p60 or 1080p30, whatever the FPGA may be capable of. Though if these rates are per TDMS channel then that's plenty for 1080p60. However, in the Digilent HDMI demo a video format of 1080p60 is shown [5]. In summary, can someone clarify what video formats and data rates the Nexys Video is capable of on HDMI input and output? Thanks in advance, Will For reference the data rate of some common HDMI formats: 720p60 - 1.45 Gbit/s (HDMI 1.0+) 1080p30 - 1.58 Gbit/s (HDMI 1.0+) 1080p60 - 3.20 Gbit/s (HDMI 1.0+) 2160p30 - 6.18 Gbit/s (HDMI 1.4+) 2160p60 - 12.54 Gbit/s (HDMI 2.0+) [1] https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf (page 50) [2] https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexysvideo_rm.pdf [3] http://www.analog.com/en/products/audio-video/hdmidvi-transmitters/ad8195.html [4] http://www.ti.com/product/tmds141 [5] https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-hdmi-demo/start
  5. macgyverque

    Multiple UARTLite Instantiation w/ Microblaze

    Trying to instantiate multiple UARTLite cores in a microblaze design using an Arty Board. For some reason, the output of both UARTLite modules is going through the same USB UART port as opposed to the second port I've configured. Any suggestions? [CONSTRAINTS] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_rxd] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN U11 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN V16 [get_ports usb_uart_bc127_rxd] [SOURCE CODE] #include "xparameters.h" #include "xstatus.h" #include "xuartlite.h" #include "xil_printf.h" /************************** Constant Definitions *****************************/ #define UARTLITE_DEVICE_ID_0 XPAR_UARTLITE_0_DEVICE_ID #define UARTLITE_DEVICE_ID_1 XPAR_UARTLITE_1_DEVICE_ID #define TEST_BUFFER_SIZE 16 int UartLitePolledExample(u16 DeviceId); /************************** Variable Definitions *****************************/ XUartLite UartLite_0; /* Instance of the UartLite Device */ XUartLite UartLite_1; /* Instance of the UartLite Device */ /* * The following buffers are used in this example to send and receive data * with the UartLite. */ u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ int main(void) { int Status; /* * Run the UartLite polled example, specify the Device ID that is * generated in xparameters.h */ Status = XUartLite_Initialize(&UartLite_0, UARTLITE_DEVICE_ID_0); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } Status = XUartLite_Initialize(&UartLite_1, UARTLITE_DEVICE_ID_1); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran Uartlite polled Example\r\n"); //XUartLite_Send(&UartLite_0, SendBuffer, TEST_BUFFER_SIZE); int temp = 80000; int simplecounter = 0; char links[] = "DIGILENT DIGILENT\n\0"; char linksx[] = "ARTY ARTY ARTY ARTY\n\0"; while (1) { if (1) { xil_printf("Cha Cha Cha.... %d\r\n", simplecounter++); XUartLite_Send(&UartLite_0, &links, TEST_BUFFER_SIZE); XUartLite_Send(&UartLite_1, &linksx, TEST_BUFFER_SIZE); temp = 80000; } } return XST_SUCCESS; } [XPARAMETERS] /* Definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0 #define XPAR_AXI_UARTLITE_0_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8 /* Definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_AXI_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_AXI_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_AXI_UARTLITE_1_DEVICE_ID 1 #define XPAR_AXI_UARTLITE_1_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_1_USE_PARITY 0 #define XPAR_AXI_UARTLITE_1_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_1_DATA_BITS 8 /******************************************************************/ /* Canonical definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID #define XPAR_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_UARTLITE_0_BAUDRATE 9600 #define XPAR_UARTLITE_0_USE_PARITY 0 #define XPAR_UARTLITE_0_ODD_PARITY 0 #define XPAR_UARTLITE_0_DATA_BITS 8 /* Canonical definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_UARTLITE_1_DEVICE_ID XPAR_AXI_UARTLITE_1_DEVICE_ID #define XPAR_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_UARTLITE_1_BAUDRATE 9600 #define XPAR_UARTLITE_1_USE_PARITY 0 #define XPAR_UARTLITE_1_ODD_PARITY 0 #define XPAR_UARTLITE_1_DATA_BITS 8
  6. I spotted a question on Stack Exchange's electronics forum regarding symbols in the A7's schematic … http://electronics.stackexchange.com/q/268746/104515 I'm not the original poster, but I'm now very curious too – what do those coloured blocks on certain groups of pins mean?
  7. Hello, i am a analog discovery user and i love the device very much but i am looking for more speed and function. ok now i am proposing a system that digilent should make,lets name it analog discovery 3. i really want more speed,better SDR and a JTAG port inbuilt instrument.