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Found 22 results

  1. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by follo
  2. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code,
  3. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high t
  4. I am seeking an FPGA-based solution to communicate with a commercial display driver via mini-LVDS, which is a unidirectional interface specification established by Texas Instruments. From my understanding of the Artix-7 documentation, transmitting mini-LVDS signals is possible by exercising the MINI_LVDS_25 I/O standard on any HR I/O bank, so long as the desired bank VCCO = 2.5V. I possess an Arty S7 board, which appears to have high-speed JA and JB PMOD ports for high-speed protocols such as LVDS. However, Vcco for bank voltages 0, 14, and 15 are set to 3.3V, but both mini-LVDS and LVDS
  5. Hello, I'm looking into storing data from an ADC system read through an FPGA to an SD card at 3.5 Mbps. I'd prefer not to use a processor. It looks like I could plug the PmodSD into a CMOD A7 (for example). I've found some discussions of directly writing to an SD card on the Digilent Forum, and some links to VHDL to do this; I especially like this code: https://github.com/xesscorp/VHDL_Lib/blob/master/SDCard.vhd?_ga=2.101734593.1593613684.1574706372-1261715882.1574452484 In this discussion: [email protected] says he has been able to write to an SD card at 8 Mbps, so that would be fas
  6. TeslaCrytpo

    CMOD S7 STP FIle

    There is a 3D stp file available for CMOD A7 board, but I do not see one for the CMOD S7 board. Is one available? Thanks. James
  7. Hi all, i tryed to do the "How To Store Your SDK Project in SPI Flash" tutorial but i do not get it to work. Everything seems to be successful, but after rebooting the CmodA7 the .elf program i created does not start. During creating the project i followed the instruction from the attached post. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start) Additional i tryed to merge the .bit and .elf file with Vivado like the tutorial (https://techmuse.in/creating-and-configuring-xilinx-fpga-with-mcs/). Programming the fpga manual works, but if
  8. We are suppose to add a library from here: https://github.com/Digilent/vivado-library/releases and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  9. Hi, I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board. But the problem is that now it is not working for another three new Artix-7 Devices which I
  10. Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]),
  11. Hello everyone! I am broadcast audio engineer (ex Harman Pro/Studer) with decent experience of complex audio/control systems and DIY enthusiast with Arduino and Raspberry type-of-toy knowledge:) I also can code PHP (Yii/Laravel), a bit of Python and .NET (WPF, Core and Web Forms). Component level repairs were more of a childhood game, but smell of flux was always somewhere near.. This time i have a goal to get familiar with FPGA world, so here I am and immediately starting a new thread regarding my project:) Cheers!
  12. I have an Arty-35 evaluation board that came with a device-locked, node-locked Vivado license. (BTW, the board and tools are very nice). Does my limited Vivado license also cover programming the Cmod A7: Breadboardable Artix-7 FPGA Module which also uses an Artix-7 A7-35T FPGA component? I think they're the same Artix-7 device, so it seems like it should work. I'd like to purchase one of these Cmod A7 FPGA DIP devices, but I want to be sure my Vivado license will cover it.
  13. http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/ Got it under student edition from the university for a course. Used for 4 months only.
  14. Hi all, I am implementing a simple parallel interface to an FT232H from FTDI to use the 60 MHz 8-bit parallel interface for training VHDL. While doing this a question popped up that I was unable to find answer to, the FT232H delivers a sampling clock to which all signals are synchronous - when sampling signals to this clock does this clock have to be routed to an MRCC pin or not? It seems that MRCC pins should be used for global clocks, but what about sampling clocks? Thanks for any clarification!
  15. Hello! I'm currently working on a project and i need to use differential signaling. I'm using Arty development platform (designed around the Artix-7™ FPGA) and I have some problems in generating the two differential signals (P and N). I used an oscilloscope to check the signal that I want to be sent (MDO) by configuring it as a single ended signal and it is correct. But when I use OBUFDS the two differential signals are logic low all time. I put the verilog code below and the .xdc file configuration. Thank you very much! Have a good day! OBUFDS #( .IOSTA
  16. Hi Everyone, I am developing a design based on ISE 14.7, Artix-7 CSG324 NEXYS4 eval board. For testing purpose, I wrote a simple clock divider code as following, but the compiler keeps warning me: Line 31(red line): Result of 32-bit expression is truncated to fit in 1-bit target. The RTL schematic looks the same as I expected, If ignore the warning and program the eval board, clock frequency wouldn't change when SW0 - SW3 input changed. I wonder if it is because of compatible issue for the compiler(most people use vivado for artix-7)? But on the Xilinx website it says the ISE wi
  17. Hello, I have ordered the Artix-7 35T "Arty" FPGA Evaluation Kit to educate FPGA design (VHDL) using Vivado tool. Today, I am looking for some starting points: tutorials, websites, books, online courses, ... All help & tips are welcome. Thanks. JrV
  18. Hello, I am following this guide to program the spi flash on the Cmod-A7 so that it can boot from spi flash and run the program in the ddr. https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start However, after flashing both parts, the bootloader is able to run but it only outputs infinite "Bootloader: Processed (0x)0000022a S-records" and my program won't run. Thanks and best regards!
  19. Hi, I am looking to buy a board of the Artix-7 family and trying to choose one between Arty, Basys 3 and Nexys 4 DDR. I have the following questions. 1. Is it true that the Vivado software that comes with Arty can only be used for one year since Arty is an evaluation board? 2. Is it possible to install the Vivado software on different computers and work on them (using the same board)? Does this behavior differ in any way among the three boards mentioned above? 3. I am confused about the number of cells in Nexys 4. On Digilent's website, it says Arty & Basys 3 both have about 33K logi
  20. The SD-card pinout for the Nexys-Video in the reference manual is copied from Nexys-DDR and is incorrect. It is impossible to complete vivado with the incorrect information because one of the incorrect pins is now a ground.
  21. I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial https://reference.digilentinc.com/nexys-video/gsmb so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video? when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref Note: some of the setting of my IP MIG In this part i connect the pins R4
  22. I'm working on a design for receving HDMI video and decided to write up my method for tuning the IDELAY and ISERDES settings to sync with the incoming stream. If you are interested, you can find it at http://hamsterworks.co.nz/mediawiki/index.php/SERDES_symbol_locking