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Found 22 results

  1. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  2. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high throughput and low latency on this board? Is it possible to extend the board with PCIe? To get the full Ethernet capacity, could you please advise if purchasing a TEMAC IP license is advised and at what price? What are the alternative options and industry standards? Many thanks YM
  3. I am seeking an FPGA-based solution to communicate with a commercial display driver via mini-LVDS, which is a unidirectional interface specification established by Texas Instruments. From my understanding of the Artix-7 documentation, transmitting mini-LVDS signals is possible by exercising the MINI_LVDS_25 I/O standard on any HR I/O bank, so long as the desired bank VCCO = 2.5V. I possess an Arty S7 board, which appears to have high-speed JA and JB PMOD ports for high-speed protocols such as LVDS. However, Vcco for bank voltages 0, 14, and 15 are set to 3.3V, but both mini-LVDS and LVDS mandate 2.5V rail voltage in 7Series devices. Is it possible to alter the feedback resistor network for FB1 (shown on pg. 10 of to convert Vcco 3.3V to 2.5V? I believe by reducing R200 from 31.6K to 21.5K, 2.5V output from channel 1 of ADP5052 is achievable. Please confirm that there are no unintended consequences here. Also, I worry about signal integrity when routing differential pairs through standard 0.1" pin headers. Is this a valid concern for my frequencies of interest (50 ~ 200MHz)? I appreciate your input.
  4. Hello, I'm looking into storing data from an ADC system read through an FPGA to an SD card at 3.5 Mbps. I'd prefer not to use a processor. It looks like I could plug the PmodSD into a CMOD A7 (for example). I've found some discussions of directly writing to an SD card on the Digilent Forum, and some links to VHDL to do this; I especially like this code: In this discussion: [email protected] says he has been able to write to an SD card at 8 Mbps, so that would be fast enough for me. However, in this discussion: BenBog says he can't write faster than 1 Mbps. Is this because he is going through a linux driver from the MicroBlaze? Once the write gets going, the SPI clock used by the SD card is 25 MHz, so I'm wondering what limits the achievable write speed to much less than 25 Mbps? Is it because the write is limited to 512 byte blocks and then you have to set up a new write sequence? If one writes to an SD card directly with vhdl through SPI you obviously don't generate a file system; I presume if you use a formatted SD card the file formatting gets overwritten. This would be fine, but I'm wondering how/if one can then read this SD card on a computer? Presumably when you plug in such a card the OS will see that the card isn't formatted and won't know what to do with it. Is there some way to still get the data off the card? thanks in advance, Paul Smith Indiana University Physics
  5. TeslaCrytpo

    CMOD S7 STP FIle

    There is a 3D stp file available for CMOD A7 board, but I do not see one for the CMOD S7 board. Is one available? Thanks. James
  6. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (, but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance.
  7. Hi all, i tryed to do the "How To Store Your SDK Project in SPI Flash" tutorial but i do not get it to work. Everything seems to be successful, but after rebooting the CmodA7 the .elf program i created does not start. During creating the project i followed the instruction from the attached post. ( Additional i tryed to merge the .bit and .elf file with Vivado like the tutorial ( Programming the fpga manual works, but if i try to write it in the flash the .elf program does not start. After programing the flash the bitstream is out of date (i don't know why). Maybe someone have an idea what i can do to get the merged bit file or mcs file on the spi-flash? Attached is my vivado project folder (
  8. We are suppose to add a library from here: and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  9. Hi, I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board. But the problem is that now it is not working for another three new Artix-7 Devices which I have bought just one month before. Same Verilog program is working in my previous three board but not working for the new three boards. Each operation, I have run 10 ring oscillator sequentially with each for 5s but after running one ring oscillator properly, then another ring oscillator has been gone to zero or sometimes not stop properly at the specific time. I have used the case statement to run individual ring oscillator. Please help me where is my main problem. I think in frequency counter function the clock from ring oscillator showing some problem but why is does not shown in other three FPGA board. The problem shows me very interesting but also painful to fix up it. Thanks
  10. Ignacas

    FPGA audio - ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  11. Hello everyone! I am broadcast audio engineer (ex Harman Pro/Studer) with decent experience of complex audio/control systems and DIY enthusiast with Arduino and Raspberry type-of-toy knowledge:) I also can code PHP (Yii/Laravel), a bit of Python and .NET (WPF, Core and Web Forms). Component level repairs were more of a childhood game, but smell of flux was always somewhere near.. This time i have a goal to get familiar with FPGA world, so here I am and immediately starting a new thread regarding my project:) Cheers!
  12. I have an Arty-35 evaluation board that came with a device-locked, node-locked Vivado license. (BTW, the board and tools are very nice). Does my limited Vivado license also cover programming the Cmod A7: Breadboardable Artix-7 FPGA Module which also uses an Artix-7 A7-35T FPGA component? I think they're the same Artix-7 device, so it seems like it should work. I'd like to purchase one of these Cmod A7 FPGA DIP devices, but I want to be sure my Vivado license will cover it.
  13. Got it under student edition from the university for a course. Used for 4 months only.
  14. Hi all, I am implementing a simple parallel interface to an FT232H from FTDI to use the 60 MHz 8-bit parallel interface for training VHDL. While doing this a question popped up that I was unable to find answer to, the FT232H delivers a sampling clock to which all signals are synchronous - when sampling signals to this clock does this clock have to be routed to an MRCC pin or not? It seems that MRCC pins should be used for global clocks, but what about sampling clocks? Thanks for any clarification!
  15. Hello! I'm currently working on a project and i need to use differential signaling. I'm using Arty development platform (designed around the Artix-7™ FPGA) and I have some problems in generating the two differential signals (P and N). I used an oscilloscope to check the signal that I want to be sent (MDO) by configuring it as a single ended signal and it is correct. But when I use OBUFDS the two differential signals are logic low all time. I put the verilog code below and the .xdc file configuration. Thank you very much! Have a good day! OBUFDS #( .IOSTANDARD("TMDS_33"), // Specify the output I/O standard .SLEW("FAST") // Specify the output slew rate ) OBUFDS_inst ( .O(ME_DIFF_P), // Diff_p output .OB(ME_DIFF_N), // Diff_n output .I(MDO) // Buffer input ); # .xdc file set_property PACKAGE_PIN U12 [get_ports ME_DIFF_P] set_property PACKAGE_PIN V12 [get_ports ME_DIFF_N] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_P] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_N] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_switching_activity -deassert_resets
  16. Hi Everyone, I am developing a design based on ISE 14.7, Artix-7 CSG324 NEXYS4 eval board. For testing purpose, I wrote a simple clock divider code as following, but the compiler keeps warning me: Line 31(red line): Result of 32-bit expression is truncated to fit in 1-bit target. The RTL schematic looks the same as I expected, If ignore the warning and program the eval board, clock frequency wouldn't change when SW0 - SW3 input changed. I wonder if it is because of compatible issue for the compiler(most people use vivado for artix-7)? But on the Xilinx website it says the ISE will support Artix-7CX7A100T. Please let me know if you guys have any suggestions, Thanks ahead. module CLKDIVIDER( input clk_i, input rst_n_i, input [3:0] divider_i, output clk_o ); reg [15:0] clk_cnt; reg clk_o_s; assign clk_o = (rst_n_i == 1'b0)? 0 : clk_o_s; always @ (posedge clk_i) begin if (rst_n_i == 1'b0) begin clk_cnt <= 0; end else begin clk_cnt <= clk_cnt + 1'b1; clk_o_s <= clk_cnt[ divider_i]; end end endmodule Updates: The code when through now without warning, but after burn the code into NEXYS4 ddr board, it is not generating the output when I change the input.
  17. Hello, I have ordered the Artix-7 35T "Arty" FPGA Evaluation Kit to educate FPGA design (VHDL) using Vivado tool. Today, I am looking for some starting points: tutorials, websites, books, online courses, ... All help & tips are welcome. Thanks. JrV
  18. Hello, I am following this guide to program the spi flash on the Cmod-A7 so that it can boot from spi flash and run the program in the ddr. However, after flashing both parts, the bootloader is able to run but it only outputs infinite "Bootloader: Processed (0x)0000022a S-records" and my program won't run. Thanks and best regards!
  19. Hi, I am looking to buy a board of the Artix-7 family and trying to choose one between Arty, Basys 3 and Nexys 4 DDR. I have the following questions. 1. Is it true that the Vivado software that comes with Arty can only be used for one year since Arty is an evaluation board? 2. Is it possible to install the Vivado software on different computers and work on them (using the same board)? Does this behavior differ in any way among the three boards mentioned above? 3. I am confused about the number of cells in Nexys 4. On Digilent's website, it says Arty & Basys 3 both have about 33K logic "cells", and Nexys 4 has about 16K logic "slices". How many logic "cells" does Nexys 4 have? Which one of these boards can support a larger design? 4. Why does Basys 3 cost more than Arty even though it has less features (like no ethernet, etc.)? Looking forward to your response. This will help me to make a decision. Thank you! P.S.: I had earlier contacted Digilent through the "Contact US" link and asked these questions, but was told some of the questions were too technical, so I need to ask them in the forum. So please help!
  20. The SD-card pinout for the Nexys-Video in the reference manual is copied from Nexys-DDR and is incorrect. It is impossible to complete vivado with the incorrect information because one of the incorrect pins is now a ground.
  21. I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video? when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref Note: some of the setting of my IP MIG In this part i connect the pins R4 and T4 in the CLK_ref_p and CLK_REF_n. but in the synthesis occurs a problem
  22. I'm working on a design for receving HDMI video and decided to write up my method for tuning the IDELAY and ISERDES settings to sync with the incoming stream. If you are interested, you can find it at