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Found 5 results

  1. Hi all, I am reposting here an issue previously published on the Xilinx forum still without a solution. I repeated the test on PicoZed 7015 board and on the Zybo as well. My system configuration is as follows: Vivado 2016.3 on a Linux Debian host Standard Zynq design over Zybo (just use ethernet and the ps7_uart) CPU0 -> baremetal "Hello World" application CPU1 -> baremetal "lwIP echo server" with lwIP library to use gem0 CPU0 is run as master CPU (and launc
  2. Although I flaunt here with other people's feathers it seemed to me a nice topic for the forum. I love practical examples for the Analog Discovery 2. I think this mix of old school technology with modern technology is fascinating, don't you think so? If you don't want this on the forum feel free to throw it off with confidence. Greetings, Hans
  3. vic

    Running XAPP1079 on Zybo

    Hi, I'm trying to run the XAPP 1079 on Zybo. As the profile is not originally made for this specific board, I had to make some changes. I follow all the insructions for the Vivado and the SDK, but in the end after the board boots from the microSD card I don't see anything in the terminal. I was wondering first if the changes that I made are correct and if anymore are needed. One specific issue I am having is that while creating an instance of the Zynq7 processor, it uses the configuration preset for the ZC702 board. Can/Should I change that? Below are the tcl scripts that i have modi
  4. vic

    Running XAPP1093 on Zybo

    I am trying to run something akin to the Xilinx 1093 profile. I want to have bare-metal apllications on both the ARM A9 and the Microblaze co-processor. In the SDK, I created a Zynq FSBL and three separate simple Hello World application projects, for CPU0, CPU1 and Microblaze. When I debug the application, I download all three of these projects to the FPGA. But I only see a Hello World from Microblaze and CPU1 on the terminal. If I don't download the CPU1 project, then I can see the Microblaze and CPU0 Hello Worlds just fine. I have attached the tcl script for the block design I used. As
  5. Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth