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Found 5 results

  1. Hi all, I am reposting here an issue previously published on the Xilinx forum still without a solution. I repeated the test on PicoZed 7015 board and on the Zybo as well. My system configuration is as follows: Vivado 2016.3 on a Linux Debian host Standard Zynq design over Zybo (just use ethernet and the ps7_uart) CPU0 -> baremetal "Hello World" application CPU1 -> baremetal "lwIP echo server" with lwIP library to use gem0 CPU0 is run as master CPU (and launching the ps7_init methods), while CPU1 is started later with USE_AMP flag activated. Goal: To have the CPU1 accessing the Ethernet with LwIP and keeping the CPU0 available for other tasks (most probable, it will run Linux later on). Issue: Whenever the USE_AMP flag is turned on on CPU1, the "LwIP echo server" did not send packages over Ethernet (verified with Wireshark) neither answer back to ping. In the other case, when USE_AMP is deactivated, the Ethernet works as expected yet CPU0 stops working (due to the SCU contention)... Have somebody face the same issue? In the attachment, you might find the reference project, with CPU0/CPU1 example application (from the XSDK template). Thank you, Luca
  2. Although I flaunt here with other people's feathers it seemed to me a nice topic for the forum. I love practical examples for the Analog Discovery 2. I think this mix of old school technology with modern technology is fascinating, don't you think so? If you don't want this on the forum feel free to throw it off with confidence. Greetings, Hans
  3. vic

    Running XAPP1079 on Zybo

    Hi, I'm trying to run the XAPP 1079 on Zybo. As the profile is not originally made for this specific board, I had to make some changes. I follow all the insructions for the Vivado and the SDK, but in the end after the board boots from the microSD card I don't see anything in the terminal. I was wondering first if the changes that I made are correct and if anymore are needed. One specific issue I am having is that while creating an instance of the Zynq7 processor, it uses the configuration preset for the ZC702 board. Can/Should I change that? Below are the tcl scripts that i have modified. I have tried running the profile both on the 2017.1 and the 2015.4 version of Vivado. It is possible that it has something to do with the standalone bsp. I have tried running a simple hello world from a single core of the ARM A9 and it runs just fine. But when I try running a simple hello world application with both the cores (essentially changing the SDK part of the XAPP), I still see nothing on the terminal.
  4. vic

    Running XAPP1093 on Zybo

    I am trying to run something akin to the Xilinx 1093 profile. I want to have bare-metal apllications on both the ARM A9 and the Microblaze co-processor. In the SDK, I created a Zynq FSBL and three separate simple Hello World application projects, for CPU0, CPU1 and Microblaze. When I debug the application, I download all three of these projects to the FPGA. But I only see a Hello World from Microblaze and CPU1 on the terminal. If I don't download the CPU1 project, then I can see the Microblaze and CPU0 Hello Worlds just fine. I have attached the tcl script for the block design I used. As far as the application projects, they are the simple auto-generated hello world .c files from the SDK. What prevents CPU0 from sending Hello World to the terminal when the project for CPU1 is also downloaded? My end goal is to run either an image processing or an encryption algorithm, that divides tasks between the two cores and Microblaze or the ARM processor in general and Microblaze. 1) Should something change or be added to the block design for this to happen? 2) Is the communication between ARM and MB achieved through functions in the .c files? design_1.tcl
  5. Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth), as well as test benches for i2s_tx and Basys3_Abacus_top. All of these files are relatively simple. In addition, I've attached the constraint file, and an image of the output, taken with my DSO NANO V3. Furthermore, I've zipped up the entire project and uploaded here: Some thoughts: Maybe SSM2518 doesn't know to generate MCLK as 4xBCLK? Faulty chip? Anyways, if one of you has the time and energy to either point out flaws in my verilog or hardware setup, I would be very grateful. TIA oscillator.v i2s_tx.v sclk_div.v i2stx_tb.v Basys3_Master.xdc Basys3_Abacus_Top.v IMG_001.BMP