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Showing results for tags 'adc1410'.
I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller_0). Up to now, I'am reading trash data from the IP output, so I suppose I've made a mistake in the connections or in the data acquisition or something else. I've not seen any example of a verilog instantiation of the IP, so please let me know if there's any out there. For making the connections, I've followed the schematic in the reference manual. I'm posting my top level design and I'm also attaching the constraint
I attempted to load the ZMod ADC1410 A/D converter for the Genesys ZU3 board IP into my Vivado design (2019.2). However, the ADC1410 controller cannot be loaded into Vivado 2019.2 because the IP does not support the Genesys board. As a result, I have a AXI interface board for a board IP that won't load. Is there an update to the Vivado IP so that the AD board will work on Genesys ZU3?