Search the Community

Showing results for tags 'adc'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

  1. Norbert96

    ADC FPGA connection

    Hi! I have been working on a digital filter in LabVIEW for and ADC called AD7402. Can somebody explain the following codesequence? I don't understand what it does. I can find all the code in the datasheet of the ADC in the attachments. WORD_CLK = output word rate */ always @ (negedge word_clk ) begin case ( dec_rate ) 16'd32:begin DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; end 16'd64:begin DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; end 16'd128:begin DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFF
  2. Hi! I want to read the output data of a delta-sigma modulation based ADC (AD7402) using NI LabVIEW FPGA. Can you help me by explaining what the Verilog code in the attached datasheet (page 17) does? AD7402.pdf
  3. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for th
  4. Hi, I am trying to characterize an ADC by applying a ramp dc value as an input and receiving the digital values in SPI (three-wire option). The Select and Clock are applied (similar to DigitalOut_SPI.py example). I have implemented the test setup in the Waveforms (Analog Discovery) and it is functional. I can see the Digital Value of the ADC both in Logic Analyser and Protocol (SPI - Spy (Three-wire)) (figs attached). I have automated the full procedure using python except the SPI part. I am interested in the first 16 bits after the Select high. I have gone though
  5. I'm a newbie here and I’m working on a inverter test bench project where I have two three-phase inverters connected through an inductive load. The idea is to emulate in real time the behave of an electrical machine. To be clearer, the first inverter is going to be tested (Device Under Test) and the second one plus the inductive load must behave like an electrical machine. To do so, we are going to use a FPGA board, which must have the following specifications: - Capable to drive both inverters switching at 50kHz (each inverter has 6 MOSFETs switching at this frequency) - 20 digital I
  6. Hi, i have been analyzing signal response from a DUT (a resonator) using network function in waveforms. For comparison, i ran the same setup and parameters on the actuation signal using a lock-in amplifier (MFLI) separately. Both responses are attached below. So far i have been getting very similiar response (from frequency and phase shift perspective), but with a significantly different amplitude. https://imgur.com/a/xlJ2DWM (for some reason i kept failing to upload directly here ) The parameters of the reference signal were: Ampltude: 3V DC-Offset: 2V Freq
  7. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? a
  8. Hi, I want to read analog data from ad1 pmod. For Vivado part, I use digilent pmod ips to connet fpga. For SDK part, I use AD1.h and AD1.c library in examples. My sensor sends to me analog values between 0-3.3V. (This is a heart rate ECG values). During using arduino, all heart beat data can be read. But I use same function for zedboard, Analog values doesnt look like arduino's. How I can configure and fix this problem? As you see ad1-zedboard connection as below.
  9. hi all, i want want to measure a voltage with the zybo and display the measured values on a screen via hdmi output. i used the hdmi passthrough projent as a start and got that working fine. know when i added the adc in vivado i get the error that the Vccs on bank 35 are incompatibele because the hdmi used 3.3V and the adc uses 1.8V. but when i look in the schematic under synthesis and look and the i/o ports i see that the hdmi aslo uses 1.8V. so why is it a problem when the adc needs 1.8V but when the hdmi needs 1.8V it works just fine.
  10. Hi! In previous topic i have asked about first start with Zynq core (i have Ettus E310 board) Now it is time for connecting ADC that is on board AD9361 . I want to get some signal and receive it via ADC - i do not understand how to connect ADC (how to edit Zynq for getting data via RF board connector (via LVDS??) https://files.ettus.com/schematics/e310/e310.pdf) I have read manual (p.34) about that ADC https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf I hope, somebody help me to edit blocks or code in Vivado and get digitalized data from A
  11. Hi all I'm currently working on a project based on ultrasound. I've created a pulsetransmitting board already which hooks into the zedboards FMC-LPC connector (I needed 64 high-speed channels), yet now I need to make a receiving side as well. Since returning signals are in the range of 250-300kHz, I was looking into ADCs of around [email protected] or 14bits. (max. 4 channels needed) Now is the problem that I can't find any spec on the frequency the zedboard PMODs can handle. Is it possible to have speeds of approx 20MHz or is this out of range of the (high-speed) PMOD connectors? Would it
  12. Hello and thanks for taking the time to read my question. I'm hoping to use the ADC functionality of the chipkituC32 but I have some questions. As I understand it, when I write the command Input = analogRead(A3) I should get an interger number 1023 /3.3 = x . However when I have no input into the A3 port, I get the constant number 788. How do I do the correct conversion? When I was sending in a DC voltage of 2 V I was getting alternating numbers between 600 and 1023 which make no sense. Also, I cannot find in the datasheet, what is the frequency to read in a signal? I found somewh
  13. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Th
  14. Hello, I am trying to interface MCP3008 with basys 3 using SPI and store the values in a FIFO and transmit the values to PC using UART. Initially, I designed for ADC to convert input waveform and display results by increment or decrements of LED's. The MCP3008 ADC clock is 1.3 MHz clock. This works and led's increment as the amplitude of the input waveform is increased from signal generator . But when i receive through UART and plot on SerialPlot , the signal is distorted please find the code for ADC below: entity ADC is port ( -- command input clo
  15. Hello, I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue. Best, Mahdi
  16. Hi, I am wondering whether the scope channel in Analog Discovery can record a voice data from a microphone.? and do signal processing such as averaging, FFT etc? Suppose, I have a mic and mic-amplifier. Can feed the output from the mic-amplifier straight to scope input? and then see the waveform in the scope mode? If so, is it then possible to save the voice data for ( say 10 seconds) and then do the processing (averaging and then to perform FFT to extract the frequency components? If so what is the best way to start? Also, if created a complex waveform in the AWG (wav
  17. hello ! i am using pmodAD5 connected with arduino uno . i am looking to use the onboard AD7193 in continuous conversion mode to measure the data , but i am unable to get the correct and desirable conversion results. Can anyone help me with this . i hereby attach the respective code and library i am using for my task. AD7193.h AD7193_Voltage_measure_final.ino AD7193.cpp
  18. Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]),
  19. Hi there, I've been using the Analog Shield with a UC32 for controlling and measuring different parameters in a physics experiment. I've noticed that for certain voltages, the DAC (and ADC) both have offsets on the order of 10 - 40 mV relative the value that they are being programmed to (or being feed to by a power supply). This offset seems to be random (in that it doesn't follow a specific trend), although it is consistent for the same ADC/ADC. I've also seen that the offset pattern is different for different DAC/ADCs on the same Analog Shield and I've also tested this on different Analog
  20. CKV

    PMOD AD1 HDL codes

    Hello, can I get the HDL files for the PMOD AD1? Exactly I need code which can take the AD1 outputs D0 or D1 to HDL module and gives me the output has 12bit number. so that I can process these 12bit numbers in subsequent modules.
  21. Hello! For a (very modest) first try with the BASYS 3 board, I'd like to measure a signal using an ADC for the BASYS 3 board I have, possibly average the signal over a set of measurements and then send this out using PWM. I'm looking for examples in VHDL, and only found one in verilog so far. And any explanation that you care to offer me. As you can tell I'm a novis and a biologist at that. I've taken (75%) of a beginners course in VHDL, but am very interested and enthusiastic. Now, hit me (with kid gloves). Thanks in advance!
  22. Hello guys, I am fairly new to FPGAs, but I have managed to get my Arty board to work with a bunch of Pmods through Vivado software with MicroBlaze. At this point, I am trying to use AXI Quad SPI for collecting data from an external ADC. I have my own 16-bit ADC (connected to a detector) which has an event flag pin that goes high when an event is detected. The flag is supposed to be latched high until the CPU responds and shifts out the 16-bit value. I wonder how can I implement such design inside my block diagram? I tried adding a SPI connector to my diagram, but as far as I see there is
  23. ATIF JAVED

    ADC DAC SELECTION

    I want to interface DAC and ADC with some fpga evaluation board My requirement of ADC and DAC is following DAC input ->sampling_rate=2MS/s frequency=455khz ADC Input ->Signal bandwidth=400khz i have no problem of resolution So someone please guide me or refer me some models of adc and dac along with some FPGA evaluation board that complete my requirements . Also refer me if anyone know about some board that have build in adc dac along with FPGA Any kind of help in this regard would be much appreciable
  24. Hello Digilent, I am just going to buy an ARTY A7 35T board and I have to interface an external ADC ADC7091R with it. I know it has an on board XADC but I need to do for some specific purpose. Now I have seen a Pmod of ADC7091 R given in its datasheet and I want to know that "DO ARTY A7 support pmod of ADC7091R". Thanks
  25. CKV

    ADC and DAC PMOD module

    Hello, Do we have any PMOD module which has both ADC and DAC in the same module?