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I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module. Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board? Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board? Thanks, Shruthi Sampathkumar.